apb-lite-slave-regfile

// APB slave with 4 word registers.
module TopModule (
    input               clk,
    input               rst,
    input               psel,
    input               penable,
    input               pwrite,
    input        [3:0]  paddr,
    input        [31:0] pwdata,
    output reg   [31:0] prdata,
    output reg          pready,
    output reg          pslverr
);

    localparam [31:0] W2_VAL = 32'h0AB15001;

    reg [31:0] reg0;       // word 0: normal R/W
    reg [7:0]  reg1_low;   // word 1: stores only low byte
    reg [31:0] reg3;       // word 3: normal R/W (one wait state)
    reg        wait_done;  // word-3: set once past the first access cycle

    wire access = psel & penable;

    // Combinational outputs. Meaningful only on access cycles; held at 0
    // otherwise and while rst is high.
    always @(*) begin
        pready  = 1'b0;
        pslverr = 1'b0;
        prdata  = 32'd0;
        if (!rst && access) begin
            if (paddr >= 4'd4) begin
                // Off-map: complete with error, no data.
                pready  = 1'b1;
                pslverr = 1'b1;
                prdata  = 32'd0;
            end else begin
                pslverr = 1'b0;
                if (paddr == 4'd3)
                    pready = wait_done ? 1'b1 : 1'b0; // one wait cycle
                else
                    pready = 1'b1;                    // mapped, no wait
                if (!pwrite) begin
                    case (paddr)
                        4'd0: prdata = reg0;
                        4'd1: prdata = {24'd0, reg1_low};
                        4'd2: prdata = W2_VAL;
                        4'd3: prdata = reg3;
                        default: prdata = 32'd0;
                    endcase
                end
            end
        end
    end

    always @(posedge clk) begin
        if (rst) begin
            reg0      <= 32'd0;
            reg1_low  <= 8'd0;
            reg3      <= 32'd0;
            wait_done <= 1'b0;
        end else begin
            // Track word-3 wait state: after the first access cycle of a
            // held word-3 transaction, mark the wait as consumed. Any drop
            // of psel/penable ends the transaction and clears it.
            if (access && paddr == 4'd3)
                wait_done <= 1'b1;
            else
                wait_done <= 1'b0;

            // Commit writes only when the access cycle actually completes
            // without error.
            if (access && pready && !pslverr && pwrite) begin
                case (paddr)
                    4'd0: reg0     <= pwdata;
                    4'd1: reg1_low <= pwdata[7:0];
                    4'd3: reg3     <= pwdata;
                    default: ; // word 2 accepted but ignored; off-map excluded
                endcase
            end
        end
    end

endmodule