stream-frame-hold

module TopModule(
  input         clk,
  input         rst,
  input         wr_i,
  input  [31:0] wr_data,
  input         wr_last_i,
  output        wr_ready_o,
  output        m_tvalid_o,
  output [31:0] m_tdata_o,
  output        m_tlast_o,
  input         m_tready_i
);

  // ---------------------------------------------------------------
  // Depth-8 FIFO storing {last, data}
  // ---------------------------------------------------------------
  reg [32:0] mem [0:7];
  reg [2:0]  wptr, rptr;
  reg [3:0]  count;

  wire fifo_full  = (count == 4'd8);
  wire fifo_empty = (count == 4'd0);

  assign wr_ready_o = ~fifo_full;

  wire push = wr_i & wr_ready_o;

  wire [32:0] rentry        = mem[rptr];
  wire        fifo_last_out = rentry[32];
  wire [31:0] fifo_data_out = rentry[31:0];

  // ---------------------------------------------------------------
  // Registered AXI-Stream master outputs
  // ---------------------------------------------------------------
  reg        m_tvalid_r;
  reg [31:0] m_tdata_r;
  reg        m_tlast_r;

  reg        cur_is_payload_last; // current loaded beat is a payload w/ last=1
  reg [1:0]  pad_count;           // pad beats remaining to emit
  reg [31:0] last_payload_data;   // data of the last-flagged payload

  assign m_tvalid_o = m_tvalid_r;
  assign m_tdata_o  = m_tdata_r;
  assign m_tlast_o  = m_tlast_r;

  // Load decisions (only when the stream register is idle)
  wire do_load      = ~m_tvalid_r;
  wire load_pad     = do_load & (pad_count != 2'd0);
  wire load_payload = do_load & (pad_count == 2'd0) & ~fifo_empty;
  wire pop          = load_payload;

  always @(posedge clk) begin
    if (rst) begin
      wptr                <= 3'd0;
      rptr                <= 3'd0;
      count               <= 4'd0;
      m_tvalid_r          <= 1'b0;
      m_tdata_r           <= 32'd0;
      m_tlast_r           <= 1'b0;
      cur_is_payload_last <= 1'b0;
      pad_count           <= 2'd0;
      last_payload_data   <= 32'd0;
    end else begin
      // ----- FIFO write -----
      if (push) begin
        mem[wptr] <= {wr_last_i, wr_data};
        wptr      <= wptr + 3'd1;
      end
      // ----- FIFO read -----
      if (pop) begin
        rptr <= rptr + 3'd1;
      end
      // ----- Occupancy: single update covering both events -----
      count <= count + (push ? 4'd1 : 4'd0) - (pop ? 4'd1 : 4'd0);

      // ----- Stream output state -----
      if (m_tvalid_r) begin
        if (m_tready_i) begin
          // Beat accepted: deassert valid (forces one idle cycle)
          m_tvalid_r <= 1'b0;
          if (cur_is_payload_last) begin
            pad_count         <= 2'd2;
            last_payload_data <= m_tdata_r;
          end
        end
        // else hold beat unchanged
      end else begin
        // Idle: load the next beat
        if (load_pad) begin
          m_tdata_r           <= last_payload_data ^ 32'h0BAD_F00D;
          m_tlast_r           <= (pad_count == 2'd1); // last=1 on 2nd pad only
          m_tvalid_r          <= 1'b1;
          cur_is_payload_last <= 1'b0;
          pad_count           <= pad_count - 2'd1;
        end else if (load_payload) begin
          m_tdata_r           <= fifo_data_out;
          m_tlast_r           <= 1'b0;             // payloads always last=0
          m_tvalid_r          <= 1'b1;
          cur_is_payload_last <= fifo_last_out;
        end
      end
    end
  end

endmodule