serial-break-resync

// UART receiver with break detection and framing-error carry-over.
//
// Frame: idle-high line, one low start bit, 8 data bits LSB-first, one high
// stop bit; each bit is BITLEN clock cycles.
module TopModule #(
    parameter BITLEN = 8
)(
    input  wire       clk,
    input  wire       rst,
    input  wire       rx_i,
    output reg  [7:0] data_o,
    output reg        valid_o,
    output reg        frame_err_o,
    output reg        break_o
);
    // Half a bit period (floored) and six full bit periods.
    localparam integer HALF   = BITLEN/2;
    localparam integer SIXBIT = 6*BITLEN;
    localparam integer CW     = $clog2(6*BITLEN+2) + 1;

    localparam [1:0] IDLE = 2'd0, RECV = 2'd1, BRK = 2'd2, RECOVER = 2'd3;

    // Two-flop synchronizer.
    reg rx_meta, rx_sync;

    reg [1:0]    state;
    reg [CW-1:0] low_cnt;    // consecutive low cycles (saturates at SIXBIT)
    reg [CW-1:0] high_cnt;   // consecutive high cycles (saturates at SIXBIT)
    reg [CW-1:0] bit_timer;  // cycles within the current bit
    reg [3:0]    bit_num;    // next bit to sample: 0..7 data, 8 = stop
    reg [7:0]    shreg;      // assembled data bits
    reg [3:0]    forced_count; // pending bytes that must report frame error

    // Combinational temporaries (assigned before use each cycle).
    reg [CW-1:0] lc, hc, bt;

    always @(posedge clk) begin
        if (rst) begin
            rx_meta      <= 1'b1;
            rx_sync      <= 1'b1;
            state        <= IDLE;
            low_cnt      <= {CW{1'b0}};
            high_cnt     <= {CW{1'b0}};
            bit_timer    <= {CW{1'b0}};
            bit_num      <= 4'd0;
            shreg        <= 8'd0;
            forced_count <= 4'd0;
            data_o       <= 8'd0;
            valid_o      <= 1'b0;
            frame_err_o  <= 1'b0;
            break_o      <= 1'b0;
        end else begin
            // Synchronize rx_i.
            rx_meta <= rx_i;
            rx_sync <= rx_meta;

            // Pulsed outputs default low each cycle.
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;

            // Saturating run-length counters on the synchronized line.
            if (rx_sync == 1'b0)
                lc = (low_cnt == SIXBIT[CW-1:0]) ? low_cnt : (low_cnt + 1'b1);
            else
                lc = {CW{1'b0}};

            if (rx_sync == 1'b1)
                hc = (high_cnt == SIXBIT[CW-1:0]) ? high_cnt : (high_cnt + 1'b1);
            else
                hc = {CW{1'b0}};

            low_cnt  <= lc;
            high_cnt <= hc;

            // ---- Break detection: preempts any in-progress frame. ----
            // Suppressed while in BRK/RECOVER (line low during recovery just
            // restarts the high count).
            if ((state == IDLE || state == RECV) && (lc == SIXBIT[CW-1:0])) begin
                break_o      <= 1'b1;
                // d = data bits the interrupted byte sampled (0 if none).
                forced_count <= (state == RECV) ? bit_num : 4'd0;
                state        <= BRK;
            end else begin
                case (state)
                    IDLE: begin
                        // Accept start when a fresh low reaches half a bit period.
                        if (rx_sync == 1'b0 && lc == HALF[CW-1:0]) begin
                            state     <= RECV;
                            bit_timer <= {CW{1'b0}};
                            bit_num   <= 4'd0;
                            shreg     <= 8'd0;
                        end
                    end

                    RECV: begin
                        bt = bit_timer + 1'b1;
                        if (bt == BITLEN[CW-1:0]) begin
                            bit_timer <= {CW{1'b0}};
                            if (bit_num < 4'd8) begin
                                // Sample a data bit at its center, LSB first.
                                shreg[bit_num] <= rx_sync;
                                bit_num        <= bit_num + 1'b1;
                            end else begin
                                // Sample the stop bit: deliver the byte.
                                valid_o     <= 1'b1;
                                data_o      <= shreg;
                                frame_err_o <= (rx_sync == 1'b0) ||
                                               (forced_count != 4'd0);
                                if (forced_count != 4'd0)
                                    forced_count <= forced_count - 1'b1;
                                bit_num <= 4'd0;
                                state   <= IDLE;
                            end
                        end else begin
                            bit_timer <= bt;
                        end
                    end

                    BRK: begin
                        // break_o stays high until the line returns high.
                        if (rx_sync == 1'b1) begin
                            break_o <= 1'b0;
                            state   <= RECOVER;
                        end
                    end

                    RECOVER: begin
                        // No start accepted until the line holds high six bit
                        // periods; any low restarts (break_o stays low).
                        if (hc == SIXBIT[CW-1:0])
                            state <= IDLE;
                    end

                    default: state <= IDLE;
                endcase
            end
        end
    end
endmodule