apb-lite-slave-regfile

module TopModule (
    input  logic        clk,
    input  logic        rst,
    input  logic        psel,
    input  logic        penable,
    input  logic        pwrite,
    input  logic [3:0]  paddr,
    input  logic [31:0] pwdata,
    output logic [31:0] prdata,
    output logic        pready,
    output logic        pslverr
);

    // Writable / stored registers
    logic [31:0] word0;
    logic [7:0]  word1_low;
    logic [31:0] word3;

    // Tracks that the single wait access cycle of the current held
    // word-3 transaction has already been observed.
    logic        word3_waited;

    localparam logic [31:0] WORD2_CONST = 32'h0AB15001;

    // Current APB access phase (setup is psel=1/penable=0)
    wire        access = psel & penable;
    wire        offmap = |paddr[3:2];      // paddr >= 4
    wire [1:0]  widx   = paddr[1:0];

    // ---------------------------------------------------------------
    // Combinational outputs
    // ---------------------------------------------------------------
    always_comb begin
        prdata  = 32'd0;
        pready  = 1'b0;
        pslverr = 1'b0;

        if (!rst && access) begin
            if (offmap) begin
                pready  = 1'b1;
                pslverr = 1'b1;
                prdata  = 32'd0;
            end else begin
                pslverr = 1'b0;
                unique case (widx)
                    2'd0: begin
                        pready = 1'b1;
                        if (!pwrite) prdata = word0;
                    end
                    2'd1: begin
                        pready = 1'b1;
                        if (!pwrite) prdata = {24'd0, word1_low};
                    end
                    2'd2: begin
                        pready = 1'b1;
                        if (!pwrite) prdata = WORD2_CONST;
                    end
                    2'd3: begin
                        pready = word3_waited;
                        if (!pwrite) prdata = word3;
                    end
                endcase
            end
        end
    end

    // ---------------------------------------------------------------
    // Sequential state
    // ---------------------------------------------------------------
    always_ff @(posedge clk) begin
        if (rst) begin
            word0        <= 32'd0;
            word1_low    <= 8'd0;
            word3        <= 32'd0;
            word3_waited <= 1'b0;
        end else begin
            // Word-3 wait tracking: set while in a word-3 access, clear
            // whenever the held transaction ends or targets another word.
            if (access && !offmap && widx == 2'd3)
                word3_waited <= 1'b1;
            else
                word3_waited <= 1'b0;

            // Writes complete only on an access cycle where pready=1 and
            // pslverr=0.  Word 2 is accepted but ignored.
            if (access && pwrite && pready && !pslverr) begin
                unique case (widx)
                    2'd0: word0     <= pwdata;
                    2'd1: word1_low <= pwdata[7:0];
                    2'd2: ;            // read-only: ignore write
                    2'd3: word3      <= pwdata;
                endcase
            end
        end
    end

endmodule