bus-slave-abort-ack

module TopModule(
    input             clk,
    input             rst,
    input             cyc_i,
    input             stb_i,
    input             we_i,
    input      [1:0]  adr_i,
    input      [15:0] dat_i,
    output            stall_o,
    output reg        ack_o,
    output reg [15:0] dat_o
);

    // Four 16-bit slots and their primed bits
    reg [15:0] slotmem [0:3];
    reg [3:0]  primed;

    // Read pipeline: accept at E -> respond at E+2
    reg        rd1_v,  rd2_v;
    reg [1:0]  rd1_adr, rd2_adr;
    reg        rd1_pr, rd2_pr;
    reg [15:0] rd1_slot,rd2_slot;

    // Write pipeline: accept at E -> commit/respond at E+3
    reg        wr1_v,  wr2_v,  wr3_v;
    reg [1:0]  wr1_adr, wr2_adr, wr3_adr;
    reg [15:0] wr1_dat, wr2_dat, wr3_dat;

    integer i;

    // Lane packing: into lane k place bit-reversed source lane (k+a) mod 4.
    // Lane j occupies bits j, j+4, j+8, j+12 (increasing bit order).
    function [15:0] mix;
        input [1:0]  a;
        input [15:0] x;
        integer k;
        integer s;
        begin
            mix = 16'h0000;
            for (k = 0; k < 4; k = k + 1) begin
                s = (k + a) % 4;
                // source lane bits (increasing): x[s], x[s+4], x[s+8], x[s+12]
                // bit-reversed -> x[s+12], x[s+8], x[s+4], x[s] into lane k
                mix[k]      = x[s + 12];
                mix[k + 4]  = x[s + 8];
                mix[k + 8]  = x[s + 4];
                mix[k + 12] = x[s];
            end
        end
    endfunction

    // Stall is asserted while a write occupies pipeline stage 2 or 3.
    assign stall_o = wr2_v | wr3_v;

    wire accept   = cyc_i & stb_i & ~stall_o;
    wire is_read  = accept & ~we_i;
    wire is_write = accept &  we_i;

    always @(posedge clk) begin
        if (rst) begin
            for (i = 0; i < 4; i = i + 1)
                slotmem[i] <= 16'h0000;
            primed   <= 4'h0;

            rd1_v <= 1'b0; rd2_v <= 1'b0;
            rd1_adr <= 2'b0; rd2_adr <= 2'b0;
            rd1_pr <= 1'b0; rd2_pr <= 1'b0;
            rd1_slot <= 16'h0000; rd2_slot <= 16'h0000;

            wr1_v <= 1'b0; wr2_v <= 1'b0; wr3_v <= 1'b0;
            wr1_adr <= 2'b0; wr2_adr <= 2'b0; wr3_adr <= 2'b0;
            wr1_dat <= 16'h0000; wr2_dat <= 16'h0000; wr3_dat <= 16'h0000;

            dat_o <= 16'h0000;
            ack_o <= 1'b0;
        end else begin
            // ---- advance read pipeline ----
            rd1_v    <= is_read;
            rd1_adr  <= adr_i;
            rd1_pr   <= primed[adr_i];
            rd1_slot <= slotmem[adr_i];
            rd2_v    <= rd1_v;
            rd2_adr  <= rd1_adr;
            rd2_pr   <= rd1_pr;
            rd2_slot <= rd1_slot;

            // ---- advance write pipeline ----
            wr1_v   <= is_write;
            wr1_adr <= adr_i;
            wr1_dat <= dat_i;
            wr2_v   <= wr1_v;
            wr2_adr <= wr1_adr;
            wr2_dat <= wr1_dat;
            wr3_v   <= wr2_v;
            wr3_adr <= wr2_adr;
            wr3_dat <= wr2_dat;

            // ---- write commit at E+3 (always commits, even if dropped) ----
            if (wr3_v) begin
                slotmem[wr3_adr] <= mix(wr3_adr, slotmem[wr3_adr]) ^ wr3_dat;
                primed[wr3_adr]  <= 1'b1;
            end

            // ---- response drive: read wins on shared edge ----
            if (cyc_i) begin
                if (rd2_v) begin
                    dat_o <= rd2_pr ? mix(rd2_adr, rd2_slot) : 16'h0000;
                    ack_o <= 1'b1;
                end else if (wr3_v) begin
                    dat_o <= mix(wr3_adr, slotmem[wr3_adr]) ^ wr3_dat;
                    ack_o <= 1'b1;
                end else begin
                    dat_o <= 16'h0000;
                    ack_o <= 1'b0;
                end
            end else begin
                dat_o <= 16'h0000;
                ack_o <= 1'b0;
            end
        end
    end

endmodule