debug-halt-step-fsm

// Control block: stops/resumes a core over a debug port.
//
// Timing calibration: the dbus read is one register stage -- an address/ren
// sampled at edge R presents data "at edge R+1". So a request sampled at
// edge N produces its first registered effect that the spec observes "at N+1".
//
//   * resume : HALTED -> RUN            (1 stage; running from G+1)
//   * step   : HALTED -> STEP_FETCH     (fetch pulse at S+1) -> HALTED (S+2)
//   * halt   : RUN -> HALT_P1 (fetch still high, seen at E+1)
//                  -> HALTED (fetch low / halted high, seen at E+2)
//
// All outputs are registered functions of the next state, so they carry the
// same single-stage latency as the dbus read.

module TopModule (
    input              clk,
    input              rst,
    input              halt_req_i,
    input              resume_req_i,
    input              step_req_i,
    input              dbus_ren_i,
    input      [1:0]   dbus_addr_i,
    output reg [7:0]   dbus_rdata_o,
    output reg         halted_o,
    output reg         fetch_o
);

    localparam [1:0] RUN        = 2'd0,
                     HALT_P1    = 2'd1,
                     HALTED     = 2'd2,
                     STEP_FETCH = 2'd3;

    reg  [1:0] state;
    reg  [1:0] nstate;

    // ---- next-state logic ----------------------------------------------
    always @(*) begin
        case (state)
            RUN:        nstate = halt_req_i ? HALT_P1 : RUN;
            HALT_P1:    nstate = HALTED;
            HALTED: begin
                if (halt_req_i && step_req_i) nstate = HALTED;      // conflict: stay halted
                else if (step_req_i)          nstate = STEP_FETCH;
                else if (resume_req_i)        nstate = RUN;
                else                          nstate = HALTED;
            end
            STEP_FETCH: nstate = HALTED;
            default:    nstate = RUN;
        endcase
    end

    // Registered outputs are a function of the next state.
    wire nfetch  = (nstate == RUN) || (nstate == HALT_P1) || (nstate == STEP_FETCH);
    wire nhalted = (nstate == HALTED);

    // ---- debug-bus memory ----------------------------------------------
    function [7:0] mem_read(input [1:0] a);
        case (a)
            2'd0:    mem_read = 8'h5A;
            2'd1:    mem_read = 8'hC3;
            2'd2:    mem_read = 8'h0F;
            default: mem_read = 8'h96;
        endcase
    endfunction

    // ---- registers ------------------------------------------------------
    always @(posedge clk) begin
        if (rst) begin
            state        <= RUN;      // internal state; outputs forced to 0 below
            fetch_o      <= 1'b0;
            halted_o     <= 1'b0;
            dbus_rdata_o <= 8'h00;
        end else begin
            state    <= nstate;
            fetch_o  <= nfetch;
            halted_o <= nhalted;

            if (dbus_ren_i) dbus_rdata_o <= mem_read(dbus_addr_i);
            else            dbus_rdata_o <= dbus_rdata_o;   // hold
        end
    end

endmodule