Write /app/dut.sv defining TopModule with ports clk, rst, op_valid_i, op_class_i[1:0], op_rd_i[1:0], op_data_i[15:0], c2_done_i, op_accept_o, wb_valid_o, wb_rd_o[1:0], wb_data_o[15:0], c2_busy_o, and inflight_o[3:0]. rst is synchronous active high and clears all slots, registered outputs, and inflight_o. op_accept_o and c2_busy_o are combinational.
There is one slot for each class 0, 1, and 2. Accept a request combinationally exactly when op_valid_i=1, its destination bit is not set in registered inflight_o, and its class slot is empty; rejected requests are dropped. Requests with op_class_i=3 are never accepted or stored. On the accepting edge, store the request and set that destination bit.
Class 0 writes back op_data_i+1 one cycle after accept. Class 1 writes back op_data_i*2 two cycles after accept. Class 2 stores op_data_i ^ 16'hffff; it becomes ready once c2_done_i is high at an edge while busy. Readiness is sticky until the writeback fires, even if c2_done_i drops. c2_busy_o is high exactly while that slot is occupied, including before an edge that writes it back.
Only one writeback may occur per cycle. Ready priority is class 0, then 1, then 2; blocked slots stay ready and are not dropped. A writeback pulses wb_valid_o for one cycle and carries the selected destination/data; on that edge the slot frees and inflight_o clears that destination. wb_rd_o and wb_data_o are checked only when wb_valid_o=1.
Do not use simulator/file-I/O tasks, preprocessor directives, DPI, force/release, or hidden grader identifiers.