serial-break-resync

// UART-style receiver with break detection and post-break frame-error tagging.
//
// Frame: 1 low start bit, 8 data bits LSB first, 1 high stop bit; each bit is
// BITLEN clock cycles.  rx_i is idle-high and is double-flop synchronized.
module TopModule #(parameter BITLEN = 16) (
    input  wire       clk,
    input  wire       rst,
    input  wire       rx_i,
    output reg  [7:0] data_o,
    output reg        valid_o,
    output reg        frame_err_o,
    output reg        break_o
);

    localparam integer HALF   = BITLEN / 2;      // half a bit period, floored
    localparam integer BREAKC = 6 * BITLEN;      // six continuous low bit periods
    localparam integer LW     = $clog2(BREAKC + 1);
    localparam integer PW     = $clog2(BITLEN + 1);

    // FSM states
    localparam [1:0] S_IDLE    = 2'd0, // idle high, waiting for a valid start
                     S_DATA    = 2'd1, // sampling 8 data bits then the stop bit
                     S_BREAK   = 2'd2, // break asserted, line still low
                     S_RECOVER = 2'd3;  // waiting for 6 high bit periods after break

    reg [1:0]        state;

    // Two-flop synchronizer for rx_i.
    reg              rx_meta, rx_sync;

    // Continuous-low / continuous-high run counters (on the synchronized line).
    reg [LW-1:0]     low_run, high_run;

    // Within-frame sample spacing and progress.
    reg [PW-1:0]     phase_cnt;   // cycles since last sample point
    reg [3:0]        data_idx;    // number of data bits sampled so far (0..8)
    reg [7:0]        shifter;     // data accumulator (LSB first)

    // Number of upcoming delivered bytes whose frame_err_o must be forced high.
    reg [3:0]        fe_pending;

    // Combinational "current" run values including this cycle.
    reg [LW-1:0]     cur_low, cur_high;

    always @(posedge clk) begin
        if (rst) begin
            rx_meta     <= 1'b1;
            rx_sync     <= 1'b1;
            state       <= S_IDLE;
            low_run     <= '0;
            high_run    <= '0;
            phase_cnt   <= '0;
            data_idx    <= '0;
            shifter     <= '0;
            fe_pending  <= '0;
            data_o      <= 8'd0;
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;
            break_o     <= 1'b0;
        end else begin
            // Synchronizer.
            rx_meta <= rx_i;
            rx_sync <= rx_meta;

            // valid_o / frame_err_o are single-cycle pulses.
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;

            // Update continuous-run counters (saturating), using the value of the
            // synchronized line this cycle.
            cur_low  = (~rx_sync) ? ((low_run  == BREAKC) ? BREAKC : (low_run  + 1'b1)) : '0;
            cur_high = ( rx_sync) ? ((high_run == BREAKC) ? BREAKC : (high_run + 1'b1)) : '0;
            low_run  <= cur_low;
            high_run <= cur_high;

            case (state)
                S_IDLE: begin
                    break_o <= 1'b0;
                    // A fresh low that reaches half a bit period accepts the start.
                    if ((HALF != 0) && (cur_low == HALF[LW-1:0])) begin
                        state     <= S_DATA;
                        phase_cnt <= '0;
                        data_idx  <= '0;
                        shifter   <= '0;
                    end
                end

                S_DATA: begin
                    if (cur_low == BREAKC[LW-1:0]) begin
                        // Six continuous low bit periods: break preempts this frame.
                        break_o    <= 1'b1;
                        fe_pending <= data_idx;   // d = data bits sampled so far
                        state      <= S_BREAK;
                    end else if (phase_cnt == (BITLEN-1)) begin
                        phase_cnt <= '0;
                        if (data_idx != 4'd8) begin
                            // Sample a data bit at its bit-period center (LSB first).
                            shifter  <= {rx_sync, shifter[7:1]};
                            data_idx <= data_idx + 1'b1;
                        end else begin
                            // Sample the stop bit: deliver the byte.
                            data_o      <= shifter;
                            valid_o     <= 1'b1;
                            frame_err_o <= (~rx_sync) | (fe_pending != 4'd0);
                            if (fe_pending != 4'd0)
                                fe_pending <= fe_pending - 1'b1;
                            state <= S_IDLE;
                        end
                    end else begin
                        phase_cnt <= phase_cnt + 1'b1;
                    end
                end

                S_BREAK: begin
                    // Break is a level: high while the line stays low, falls on high.
                    if (rx_sync) begin
                        break_o <= 1'b0;
                        state   <= S_RECOVER;   // now require 6 high bit periods
                    end else begin
                        break_o <= 1'b1;
                    end
                end

                S_RECOVER: begin
                    // No start accepted, break stays low; any low restarts the count.
                    break_o <= 1'b0;
                    if (cur_high == BREAKC[LW-1:0])
                        state <= S_IDLE;
                end

                default: state <= S_IDLE;
            endcase
        end
    end

endmodule