bus-slave-abort-ack

module TopModule(
  input             clk,
  input             rst,
  input             cyc_i,
  input             stb_i,
  input             we_i,
  input      [1:0]  adr_i,
  input      [15:0] dat_i,
  output reg        stall_o,
  output reg        ack_o,
  output reg [15:0] dat_o
);

  // storage: four 16-bit slots, one primed bit each
  reg [15:0] slots [0:3];
  reg [3:0]  primed;

  // read pipeline (accept at E -> respond at E+2): two stages
  reg        rd0_v, rd1_v;
  reg [1:0]  rd0_adr, rd1_adr;
  reg [15:0] rd0_dat, rd1_dat;
  reg        rd0_pr, rd1_pr;

  // write pipeline (accept at E -> commit/respond at E+3): three stages
  reg        wr0_v, wr1_v, wr2_v;
  reg [1:0]  wr0_adr, wr1_adr, wr2_adr;
  reg [15:0] wr0_dat, wr1_dat, wr2_dat;

  // mix(a,x): into lane k pack the bit-reversed source lane (k+a) mod 4.
  // lane k occupies bit positions k, k+4, k+8, k+12 in increasing order.
  function [15:0] mixf;
    input [1:0]  a;
    input [15:0] x;
    integer k, i, s;
    reg [15:0] r;
    begin
      r = 16'b0;
      for (k = 0; k < 4; k = k + 1) begin
        s = (k + a) & 3;
        for (i = 0; i < 4; i = i + 1) begin
          r[k + 4*i] = x[s + 4*(3-i)];
        end
      end
      mixf = r;
    end
  endfunction

  wire accept       = cyc_i & stb_i & ~stall_o;
  wire accept_read  = accept & ~we_i;
  wire accept_write = accept &  we_i;

  reg [15:0] newslot;
  reg        read_fires, write_fires;
  integer    j;

  always @(posedge clk) begin
    if (rst) begin
      for (j = 0; j < 4; j = j + 1) slots[j] <= 16'b0;
      primed  <= 4'b0;
      rd0_v   <= 1'b0; rd1_v <= 1'b0;
      wr0_v   <= 1'b0; wr1_v <= 1'b0; wr2_v <= 1'b0;
      stall_o <= 1'b0;
      ack_o   <= 1'b0;
      dat_o   <= 16'b0;
      rd0_adr <= 2'b0; rd1_adr <= 2'b0;
      rd0_dat <= 16'b0; rd1_dat <= 16'b0;
      rd0_pr  <= 1'b0; rd1_pr <= 1'b0;
      wr0_adr <= 2'b0; wr1_adr <= 2'b0; wr2_adr <= 2'b0;
      wr0_dat <= 16'b0; wr1_dat <= 16'b0; wr2_dat <= 16'b0;
    end else begin
      // fire signals derived from pre-edge pipeline state
      read_fires  = rd1_v;
      write_fires = wr2_v;

      // stall is high after E+1 and E+2 of an accepted write
      stall_o <= wr0_v | wr1_v;

      // read pipeline: shift then load; captures pre-edge slot + primed
      rd1_v   <= rd0_v;
      rd1_adr <= rd0_adr;
      rd1_dat <= rd0_dat;
      rd1_pr  <= rd0_pr;
      rd0_v   <= accept_read;
      rd0_adr <= adr_i;
      rd0_dat <= slots[adr_i];
      rd0_pr  <= primed[adr_i];

      // write pipeline: shift then load captured adr + data
      wr2_v   <= wr1_v; wr2_adr <= wr1_adr; wr2_dat <= wr1_dat;
      wr1_v   <= wr0_v; wr1_adr <= wr0_adr; wr1_dat <= wr0_dat;
      wr0_v   <= accept_write;
      wr0_adr <= adr_i;
      wr0_dat <= dat_i;

      // committed value uses pre-edge slot value
      newslot = mixf(wr2_adr, slots[wr2_adr]) ^ wr2_dat;

      // commit is unconditional (dropped writes still commit)
      if (write_fires) begin
        slots[wr2_adr]  <= newslot;
        primed[wr2_adr] <= 1'b1;
      end

      // response outputs: read wins on shared edge; ack only when cyc_i high
      if (read_fires) begin
        if (cyc_i) begin
          ack_o <= 1'b1;
          dat_o <= rd1_pr ? mixf(rd1_adr, rd1_dat) : 16'b0;
        end else begin
          ack_o <= 1'b0;
          dat_o <= 16'b0;
        end
      end else if (write_fires) begin
        if (cyc_i) begin
          ack_o <= 1'b1;
          dat_o <= newslot;
        end else begin
          ack_o <= 1'b0;
          dat_o <= 16'b0;
        end
      end else begin
        ack_o <= 1'b0;
        dat_o <= 16'b0;
      end
    end
  end

endmodule