tests/test.sh exit code (0 → resolved); the classification below is post-hoc and cannot change it.pwd && rg --files -g '!*~'
Chunk ID: ce66d7 Wall time: 0.0000 seconds Process exited with code 0 Original token count: 19 Output: /work rtr_core/rtl/rtr_top.sv rtr_core/rtl/rtr_pkg.sv rtr_core/rtl/rtr.sv
sed -n '1,220p' rtl/rtr.sv
Chunk ID: 96430f Wall time: 0.0001 seconds Process exited with code 2 Original token count: 14 Output: sed: can't read rtl/rtr.sv: No such file or directory
find . -maxdepth 3 -type f \( -name '*.sv' -o -name '*.v' -o -name 'Makefile' -o -name '*.mk' \) -print
Chunk ID: cbe6b5 Wall time: 0.0000 seconds Process exited with code 0 Original token count: 19 Output: ./rtr_core/rtl/rtr.sv ./rtr_core/rtl/rtr_pkg.sv ./rtr_core/rtl/rtr_top.sv
sed -n '1,220p' rtr_core/rtl/rtr.sv
Chunk ID: 29d3a1
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 767
Output:
//==============================================================================
// rtr.sv
//
// Instruction-retire commit handshake.
//
// ---------------------------------------------------------------------------
// >>> IMPLEMENTATION REQUIRED <<<
//
// The module ports, parameters and the state registers are provided. The
// control FSM, the latency counter and the outputs are left as a TODO and
// currently drive constant zeros, so the block never accepts or retires and
// the verifier FAILS.
//
// Implement the behaviour described in instruction.md. Do NOT change the
// module name, the port list, or the parameter list.
//
// iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
// function-call result) is a syntax error under `iverilog -g2012`. Index only
// named signals, and do any bit work that needs an intermediate value inside a
// `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps
module rtr #(
parameter DW = 8,
parameter K = 3,
parameter TRAPCODE = 8'hEE
) (
input logic clk,
input logic rst_n,
input logic req,
input logic [DW-1:0] op,
input logic trap,
output logic accept,
output logic busy,
output logic done,
output logic [DW-1:0] result
);
// ---------------------------------------------------------------------------
// State registers (provided). Use these (and add your own as needed) to track
// where in a retire the block is and the payload captured at accept time.
// ---------------------------------------------------------------------------
logic [1:0] phase; // control state
logic [DW-1:0] latch; // payload captured at accept
logic [3:0] cnt; // latency counter
// ===========================================================================
// TODO: IMPLEMENT THE RETIRE HANDSHAKE.
// * accept a req only while ready; pulse accept for one clk and capture op;
// * drive busy, done and result with the disclosed latencies and values;
// * honour the trap pre-empt and the mandatory idle edge;
// * asynchronous active-low reset clears all state and outputs.
//
// The placeholder below keeps the module compilable but INCORRECT.
// ===========================================================================
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
phase <= 2'd0;
latch <= '0;
cnt <= '0;
end else begin
// TODO: replace with the real control + datapath.
phase <= phase;
latch <= latch;
cnt <= cnt;
end
end
// TODO: replace these placeholder outputs with the real ones.
assign accept = 1'b0;
assign busy = 1'b0;
assign done = 1'b0;
assign result = '0;
endmodule : rtr
sed -n '1,220p' rtr_core/rtl/rtr_pkg.sv
Chunk ID: d57c75 Wall time: 0.0000 seconds Process exited with code 0 Original token count: 236 Output: //============================================================================== // rtr_pkg.sv // // Shared geometry for the instruction-retire commit handshake. The block latches // an 8-bit payload at accept time, counts a fixed latency, and drives a one-cycle // done strobe with either the latched payload or a masked trap code. Parameters // are declared without an explicit data type for broad simulator compatibility // (Icarus Verilog 11); they default to integer constants, which is sufficient // here. // // DO NOT change this file. //============================================================================== `ifndef RTR_PKG_SV `define RTR_PKG_SV package rtr_pkg; localparam DW = 8; // payload word width localparam K = 3; // normal retire latency (accept -> done edges) localparam TRAPCODE = 8'hEE; // masked payload driven on a trapped retire endpackage : rtr_pkg `endif // RTR_PKG_SV
sed -n '1,220p' rtr_core/rtl/rtr_top.sv
Chunk ID: 4832f1
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 334
Output:
//==============================================================================
// rtr_top.sv
//
// Thin integration wrapper. The verification environment drives this wrapper so
// that the instantiation wiring is exercised alongside the retire block itself.
// It instantiates rtr with the project-default geometry from rtr_pkg.
//
// DO NOT change this file.
//==============================================================================
`timescale 1ns/1ps
`include "rtr_pkg.sv"
module rtr_top (
input logic clk,
input logic rst_n,
input logic req,
input logic [rtr_pkg::DW-1:0] op,
input logic trap,
output logic accept,
output logic busy,
output logic done,
output logic [rtr_pkg::DW-1:0] result
);
// Bare instantiation: the block carries its own default geometry, so a
// submission needs no parameter override to elaborate correctly.
rtr u_rtr (
.clk (clk),
.rst_n (rst_n),
.req (req),
.op (op),
.trap (trap),
.accept (accept),
.busy (busy),
.done (done),
.result (result)
);
endmodule : rtr_top
find rtr_core -maxdepth 4 -type f -print
Chunk ID: 9bffd2 Wall time: 0.0000 seconds Process exited with code 0 Original token count: 17 Output: rtr_core/rtl/rtr.sv rtr_core/rtl/rtr_pkg.sv rtr_core/rtl/rtr_top.sv
*** Begin Patch
*** Update File: /work/rtr_core/rtl/rtr.sv
@@
logic [1:0] phase; // control state
logic [DW-1:0] latch; // payload captured at accept
logic [3:0] cnt; // latency counter
+
+ localparam logic [1:0] PH_IDLE = 2'd0;
+ localparam logic [1:0] PH_RUN = 2'd1;
+ localparam logic [1:0] PH_TRAP = 2'd2;
+ localparam logic [1:0] PH_REST = 2'd3;
// ===========================================================================
@@
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
- phase <= 2'd0;
- latch <= '0;
- cnt <= '0;
+ phase <= PH_IDLE;
+ latch <= '0;
+ cnt <= '0;
+ accept <= 1'b0;
+ busy <= 1'b0;
+ done <= 1'b0;
+ result <= '0;
end else begin
- // TODO: replace with the real control + datapath.
- phase <= phase;
- latch <= latch;
- cnt <= cnt;
+ accept <= 1'b0;
+ busy <= 1'b0;
+ done <= 1'b0;
+ result <= '0;
+
+ unique case (phase)
+ PH_IDLE: begin
+ cnt <= '0;
+ if (req) begin
+ phase <= PH_RUN;
+ latch <= op;
+ cnt <= 4'd1;
+ accept <= 1'b1;
+ end
+ end
+
+ PH_RUN: begin
+ if (cnt >= K[3:0]) begin
+ phase <= PH_REST;
+ cnt <= '0;
+ done <= 1'b1;
+ result <= latch;
+ end else begin
+ busy <= 1'b1;
+ if (trap) begin
+ phase <= PH_TRAP;
+ cnt <= '0;
+ end else begin
+ cnt <= cnt + 4'd1;
+ end
+ end
+ end
+
+ PH_TRAP: begin
+ phase <= PH_REST;
+ cnt <= '0;
+ done <= 1'b1;
+ result <= TRAPCODE[DW-1:0];
+ end
+
+ PH_REST: begin
+ phase <= PH_IDLE;
+ cnt <= '0;
+ end
+
+ default: begin
+ phase <= PH_IDLE;
+ latch <= '0;
+ cnt <= '0;
+ end
+ endcase
end
end
-
- // TODO: replace these placeholder outputs with the real ones.
- assign accept = 1'b0;
- assign busy = 1'b0;
- assign done = 1'b0;
- assign result = '0;
endmodule : rtr
*** End Patch
Exit code: 0
Wall time: 0 seconds
Output:
Success. Updated the following files:
M /work/rtr_core/rtl/rtr.sv
*** Begin Patch
*** Update File: /work/rtr_core/rtl/rtr.sv
@@
localparam logic [1:0] PH_IDLE = 2'd0;
localparam logic [1:0] PH_RUN = 2'd1;
localparam logic [1:0] PH_TRAP = 2'd2;
localparam logic [1:0] PH_REST = 2'd3;
+ localparam logic [3:0] K_CNT = K;
+ localparam logic [DW-1:0] TRAP_VALUE = TRAPCODE;
@@
end
PH_RUN: begin
- if (cnt >= K[3:0]) begin
+ if (cnt >= K_CNT) begin
phase <= PH_REST;
cnt <= '0;
done <= 1'b1;
@@
PH_TRAP: begin
phase <= PH_REST;
cnt <= '0;
done <= 1'b1;
- result <= TRAPCODE[DW-1:0];
+ result <= TRAP_VALUE;
end
*** End Patch
Exit code: 0
Wall time: 0 seconds
Output:
Success. Updated the following files:
M /work/rtr_core/rtl/rtr.sv
iverilog -g2012 -I rtr_core/rtl -o /tmp/rtr_compile.vvp rtr_core/rtl/rtr_pkg.sv rtr_core/rtl/rtr.sv rtr_core/rtl/rtr_top.sv
Chunk ID: 1ee1c3 Wall time: 0.0000 seconds Process exited with code 0 Original token count: 21 Output: rtr_core/rtl/rtr.sv:80: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
git diff -- rtr_core/rtl/rtr.sv
Chunk ID: fcc4e1 Wall time: 0.0000 seconds Process exited with code 127 Original token count: 11 Output: /bin/bash: line 1: git: command not found
*** Begin Patch *** Update File: /work/rtr_core/rtl/rtr.sv @@ - unique case (phase) + case (phase) *** End Patch Exit code: 0 Wall time: 0 seconds Output: Success. Updated the following files: M /work/rtr_core/rtl/rtr.sv
*** Begin Patch
*** Add File: /tmp/rtr_tb.sv
+`timescale 1ns/1ps
+
+module tb;
+ logic clk;
+ logic rst_n;
+ logic req;
+ logic [7:0] op;
+ logic trap;
+ logic accept;
+ logic busy;
+ logic done;
+ logic [7:0] result;
+ integer edge;
+
+ rtr dut (
+ .clk(clk),
+ .rst_n(rst_n),
+ .req(req),
+ .op(op),
+ .trap(trap),
+ .accept(accept),
+ .busy(busy),
+ .done(done),
+ .result(result)
+ );
+
+ initial clk = 1'b0;
+ always #5 clk = ~clk;
+
+ task automatic check(
+ input integer e,
+ input logic exp_accept,
+ input logic exp_busy,
+ input logic exp_done,
+ input logic [7:0] exp_result
+ );
+ begin
+ @(negedge clk);
+ if (accept !== exp_accept || busy !== exp_busy ||
+ done !== exp_done || result !== exp_result) begin
+ $display("FAIL edge %0d got a=%0b b=%0b d=%0b r=%02h exp a=%0b b=%0b d=%0b r=%02h",
+ e, accept, busy, done, result,
+ exp_accept, exp_busy, exp_done, exp_result);
+ $finish;
+ end
+ end
+ endtask
+
+ initial begin
+ rst_n = 1'b0;
+ req = 1'b0;
+ op = 8'h00;
+ trap = 1'b0;
+
+ repeat (2) @(posedge clk);
+ rst_n = 1'b1;
+
+ req = 1'b1;
+ op = 8'hA5;
+ @(posedge clk); check(0, 1'b1, 1'b0, 1'b0, 8'h00);
+ op = 8'h11;
+ @(posedge clk); check(1, 1'b0, 1'b1, 1'b0, 8'h00);
+ @(posedge clk); check(2, 1'b0, 1'b1, 1'b0, 8'h00);
+ @(posedge clk); check(3, 1'b0, 1'b0, 1'b1, 8'hA5);
+ @(posedge clk); check(4, 1'b0, 1'b0, 1'b0, 8'h00);
+ op = 8'h3C;
+ @(posedge clk); check(5, 1'b1, 1'b0, 1'b0, 8'h00);
+ @(posedge clk); check(6, 1'b0, 1'b1, 1'b0, 8'h00);
+ @(posedge clk); check(7, 1'b0, 1'b1, 1'b0, 8'h00);
+ @(posedge clk); check(8, 1'b0, 1'b0, 1'b1, 8'h3C);
+
+ req = 1'b0;
+ @(posedge clk); check(9, 1'b0, 1'b0, 1'b0, 8'h00);
+ op = 8'h55;
+ req = 1'b1;
+ @(posedge clk); check(10, 1'b1, 1'b0, 1'b0, 8'h00);
+ trap = 1'b1;
+ @(posedge clk); check(11, 1'b0, 1'b1, 1'b0, 8'h00);
+ trap = 1'b0;
+ @(posedge clk); check(12, 1'b0, 1'b0, 1'b1, 8'hEE);
+ @(posedge clk); check(13, 1'b0, 1'b0, 1'b0, 8'h00);
+
+ op = 8'h66;
+ @(posedge clk); check(14, 1'b1, 1'b0, 1'b0, 8'h00);
+ @(posedge clk); check(15, 1'b0, 1'b1, 1'b0, 8'h00);
+ @(posedge clk); check(16, 1'b0, 1'b1, 1'b0, 8'h00);
+ trap = 1'b1;
+ @(posedge clk); check(17, 1'b0, 1'b0, 1'b1, 8'h66);
+
+ $display("PASS");
+ $finish;
+ end
+endmodule
*** End Patch
Exit code: 0
Wall time: 0 seconds
Output:
Success. Updated the following files:
A /tmp/rtr_tb.sv
iverilog -g2012 -I rtr_core/rtl -o /tmp/rtr_compile.vvp rtr_core/rtl/rtr_pkg.sv rtr_core/rtl/rtr.sv rtr_core/rtl/rtr_top.sv
Chunk ID: e40e69 Wall time: 0.0000 seconds Process exited with code 0 Original token count: 0 Output:
iverilog -g2012 -I rtr_core/rtl -o /tmp/rtr_tb.vvp rtr_core/rtl/rtr.sv /tmp/rtr_tb.sv && vvp /tmp/rtr_tb.vvp
Chunk ID: 08a0b4 Wall time: 0.0000 seconds Process exited with code 2 Original token count: 25 Output: /tmp/rtr_tb.sv:13: syntax error /tmp/rtr_tb.sv:13: error: syntax error in integer variable list.
sed -n '1,180p' rtr_core/rtl/rtr.sv
Chunk ID: 57fdfe
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 1054
Output:
//==============================================================================
// rtr.sv
//
// Instruction-retire commit handshake.
//
// ---------------------------------------------------------------------------
// >>> IMPLEMENTATION REQUIRED <<<
//
// The module ports, parameters and the state registers are provided. The
// control FSM, the latency counter and the outputs are left as a TODO and
// currently drive constant zeros, so the block never accepts or retires and
// the verifier FAILS.
//
// Implement the behaviour described in instruction.md. Do NOT change the
// module name, the port list, or the parameter list.
//
// iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
// function-call result) is a syntax error under `iverilog -g2012`. Index only
// named signals, and do any bit work that needs an intermediate value inside a
// `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps
module rtr #(
parameter DW = 8,
parameter K = 3,
parameter TRAPCODE = 8'hEE
) (
input logic clk,
input logic rst_n,
input logic req,
input logic [DW-1:0] op,
input logic trap,
output logic accept,
output logic busy,
output logic done,
output logic [DW-1:0] result
);
// ---------------------------------------------------------------------------
// State registers (provided). Use these (and add your own as needed) to track
// where in a retire the block is and the payload captured at accept time.
// ---------------------------------------------------------------------------
logic [1:0] phase; // control state
logic [DW-1:0] latch; // payload captured at accept
logic [3:0] cnt; // latency counter
localparam logic [1:0] PH_IDLE = 2'd0;
localparam logic [1:0] PH_RUN = 2'd1;
localparam logic [1:0] PH_TRAP = 2'd2;
localparam logic [1:0] PH_REST = 2'd3;
localparam logic [3:0] K_CNT = K;
localparam logic [DW-1:0] TRAP_VALUE = TRAPCODE;
// ===========================================================================
// TODO: IMPLEMENT THE RETIRE HANDSHAKE.
// * accept a req only while ready; pulse accept for one clk and capture op;
// * drive busy, done and result with the disclosed latencies and values;
// * honour the trap pre-empt and the mandatory idle edge;
// * asynchronous active-low reset clears all state and outputs.
//
// The placeholder below keeps the module compilable but INCORRECT.
// ===========================================================================
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
phase <= PH_IDLE;
latch <= '0;
cnt <= '0;
accept <= 1'b0;
busy <= 1'b0;
done <= 1'b0;
result <= '0;
end else begin
accept <= 1'b0;
busy <= 1'b0;
done <= 1'b0;
result <= '0;
case (phase)
PH_IDLE: begin
cnt <= '0;
if (req) begin
phase <= PH_RUN;
latch <= op;
cnt <= 4'd1;
accept <= 1'b1;
end
end
PH_RUN: begin
if (cnt >= K_CNT) begin
phase <= PH_REST;
cnt <= '0;
done <= 1'b1;
result <= latch;
end else begin
busy <= 1'b1;
if (trap) begin
phase <= PH_TRAP;
cnt <= '0;
end else begin
cnt <= cnt + 4'd1;
end
end
end
PH_TRAP: begin
phase <= PH_REST;
cnt <= '0;
done <= 1'b1;
result <= TRAP_VALUE;
end
PH_REST: begin
phase <= PH_IDLE;
cnt <= '0;
end
default: begin
phase <= PH_IDLE;
latch <= '0;
cnt <= '0;
end
endcase
end
end
endmodule : rtr
*** Begin Patch *** Update File: /work/rtr_core/rtl/rtr.sv @@ - // =========================================================================== - // TODO: IMPLEMENT THE RETIRE HANDSHAKE. - // * accept a req only while ready; pulse accept for one clk and capture op; - // * drive busy, done and result with the disclosed latencies and values; - // * honour the trap pre-empt and the mandatory idle edge; - // * asynchronous active-low reset clears all state and outputs. - // - // The placeholder below keeps the module compilable but INCORRECT. - // =========================================================================== + // =========================================================================== + // Registered retire handshake. + // =========================================================================== *** End Patch Exit code: 0 Wall time: 0 seconds Output: Success. Updated the following files: M /work/rtr_core/rtl/rtr.sv
*** Begin Patch *** Update File: /tmp/rtr_tb.sv @@ - integer edge; - *** End Patch Exit code: 0 Wall time: 0 seconds Output: Success. Updated the following files: M /tmp/rtr_tb.sv
iverilog -g2012 -I rtr_core/rtl -o /tmp/rtr_compile.vvp rtr_core/rtl/rtr_pkg.sv rtr_core/rtl/rtr.sv rtr_core/rtl/rtr_top.sv
Chunk ID: 9fb768 Wall time: 0.0000 seconds Process exited with code 0 Original token count: 0 Output:
iverilog -g2012 -I rtr_core/rtl -o /tmp/rtr_tb.vvp rtr_core/rtl/rtr.sv /tmp/rtr_tb.sv && vvp /tmp/rtr_tb.vvp
Chunk ID: 074f70 Wall time: 0.0000 seconds Process exited with code 0 Original token count: 14 Output: FAIL edge 0 got a=0 b=1 d=0 r=00 exp a=1 b=0 d=0 r=00
sed -n '1,170p' rtr_core/rtl/rtr.sv
Chunk ID: 44fa25
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 960
Output:
//==============================================================================
// rtr.sv
//
// Instruction-retire commit handshake.
//
// ---------------------------------------------------------------------------
// >>> IMPLEMENTATION REQUIRED <<<
//
// The module ports, parameters and the state registers are provided. The
// control FSM, the latency counter and the outputs are left as a TODO and
// currently drive constant zeros, so the block never accepts or retires and
// the verifier FAILS.
//
// Implement the behaviour described in instruction.md. Do NOT change the
// module name, the port list, or the parameter list.
//
// iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
// function-call result) is a syntax error under `iverilog -g2012`. Index only
// named signals, and do any bit work that needs an intermediate value inside a
// `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps
module rtr #(
parameter DW = 8,
parameter K = 3,
parameter TRAPCODE = 8'hEE
) (
input logic clk,
input logic rst_n,
input logic req,
input logic [DW-1:0] op,
input logic trap,
output logic accept,
output logic busy,
output logic done,
output logic [DW-1:0] result
);
// ---------------------------------------------------------------------------
// State registers (provided). Use these (and add your own as needed) to track
// where in a retire the block is and the payload captured at accept time.
// ---------------------------------------------------------------------------
logic [1:0] phase; // control state
logic [DW-1:0] latch; // payload captured at accept
logic [3:0] cnt; // latency counter
localparam logic [1:0] PH_IDLE = 2'd0;
localparam logic [1:0] PH_RUN = 2'd1;
localparam logic [1:0] PH_TRAP = 2'd2;
localparam logic [1:0] PH_REST = 2'd3;
localparam logic [3:0] K_CNT = K;
localparam logic [DW-1:0] TRAP_VALUE = TRAPCODE;
// ===========================================================================
// Registered retire handshake.
// ===========================================================================
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
phase <= PH_IDLE;
latch <= '0;
cnt <= '0;
accept <= 1'b0;
busy <= 1'b0;
done <= 1'b0;
result <= '0;
end else begin
accept <= 1'b0;
busy <= 1'b0;
done <= 1'b0;
result <= '0;
case (phase)
PH_IDLE: begin
cnt <= '0;
if (req) begin
phase <= PH_RUN;
latch <= op;
cnt <= 4'd1;
accept <= 1'b1;
end
end
PH_RUN: begin
if (cnt >= K_CNT) begin
phase <= PH_REST;
cnt <= '0;
done <= 1'b1;
result <= latch;
end else begin
busy <= 1'b1;
if (trap) begin
phase <= PH_TRAP;
cnt <= '0;
end else begin
cnt <= cnt + 4'd1;
end
end
end
PH_TRAP: begin
phase <= PH_REST;
cnt <= '0;
done <= 1'b1;
result <= TRAP_VALUE;
end
PH_REST: begin
phase <= PH_IDLE;
cnt <= '0;
end
default: begin
phase <= PH_IDLE;
latch <= '0;
cnt <= '0;
end
endcase
end
end
endmodule : rtr
*** Begin Patch
*** Update File: /tmp/rtr_tb.sv
@@
- repeat (2) @(posedge clk);
+ repeat (2) @(posedge clk);
+ @(negedge clk);
rst_n = 1'b1;
req = 1'b1;
*** End Patch
Exit code: 0
Wall time: 0 seconds
Output:
Success. Updated the following files:
M /tmp/rtr_tb.sv
iverilog -g2012 -I rtr_core/rtl -o /tmp/rtr_compile.vvp rtr_core/rtl/rtr_pkg.sv rtr_core/rtl/rtr.sv rtr_core/rtl/rtr_top.sv
Chunk ID: 7fa198 Wall time: 0.0000 seconds Process exited with code 0 Original token count: 0 Output:
iverilog -g2012 -I rtr_core/rtl -o /tmp/rtr_tb.vvp rtr_core/rtl/rtr.sv /tmp/rtr_tb.sv && vvp /tmp/rtr_tb.vvp
Chunk ID: 9bacee Wall time: 0.0000 seconds Process exited with code 0 Original token count: 2 Output: PASS
nl -ba rtr_core/rtl/rtr.sv | sed -n '35,135p'
Chunk ID: c9a16f
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 766
Output:
35 output logic accept,
36 output logic busy,
37 output logic done,
38 output logic [DW-1:0] result
39 );
40
41 // ---------------------------------------------------------------------------
42 // State registers (provided). Use these (and add your own as needed) to track
43 // where in a retire the block is and the payload captured at accept time.
44 // ---------------------------------------------------------------------------
45 logic [1:0] phase; // control state
46 logic [DW-1:0] latch; // payload captured at accept
47 logic [3:0] cnt; // latency counter
48
49 localparam logic [1:0] PH_IDLE = 2'd0;
50 localparam logic [1:0] PH_RUN = 2'd1;
51 localparam logic [1:0] PH_TRAP = 2'd2;
52 localparam logic [1:0] PH_REST = 2'd3;
53 localparam logic [3:0] K_CNT = K;
54 localparam logic [DW-1:0] TRAP_VALUE = TRAPCODE;
55
56 // ===========================================================================
57 // Registered retire handshake.
58 // ===========================================================================
59 always_ff @(posedge clk or negedge rst_n) begin
60 if (!rst_n) begin
61 phase <= PH_IDLE;
62 latch <= '0;
63 cnt <= '0;
64 accept <= 1'b0;
65 busy <= 1'b0;
66 done <= 1'b0;
67 result <= '0;
68 end else begin
69 accept <= 1'b0;
70 busy <= 1'b0;
71 done <= 1'b0;
72 result <= '0;
73
74 case (phase)
75 PH_IDLE: begin
76 cnt <= '0;
77 if (req) begin
78 phase <= PH_RUN;
79 latch <= op;
80 cnt <= 4'd1;
81 accept <= 1'b1;
82 end
83 end
84
85 PH_RUN: begin
86 if (cnt >= K_CNT) begin
87 phase <= PH_REST;
88 cnt <= '0;
89 done <= 1'b1;
90 result <= latch;
91 end else begin
92 busy <= 1'b1;
93 if (trap) begin
94 phase <= PH_TRAP;
95 cnt <= '0;
96 end else begin
97 cnt <= cnt + 4'd1;
98 end
99 end
100 end
101
102 PH_TRAP: begin
103 phase <= PH_REST;
104 cnt <= '0;
105 done <= 1'b1;
106 result <= TRAP_VALUE;
107 end
108
109 PH_REST: begin
110 phase <= PH_IDLE;
111 cnt <= '0;
112 end
113
114 default: begin
115 phase <= PH_IDLE;
116 latch <= '0;
117 cnt <= '0;
118 end
119 endcase
120 end
121 end
122
123 endmodule : rtr
No file changes, the agent left the workspace untouched.
test.sh: compiling with iverilog... ----- iverilog output ----- --------------------------- test.sh: running simulation with vvp... ----- simulation output ----- INFO samples=438 amiss=0 bmiss=0 dmiss=0 rmiss=0 SAMPLES=438 ALL TESTS PASSED ----------------------------- test.sh: PASS - 438 samples, no mismatches
Reproduce this trial: git checkout 2f94510 && PYTHONPATH=src python3 scripts/build_site.py , then open trial/trial_eb35fd86efe04f94. Re-running the agent live requires EVAL_PLATFORM_ENABLE_OAUTH_SMOKE=1 and is non-deterministic.
Trial trial_eb35fd86efe04f94 · verifier authoritative; classifier explanatory.