debug-halt-step-fsm

module TopModule (
    input  wire       clk,
    input  wire       rst,
    input  wire       halt_req_i,
    input  wire       resume_req_i,
    input  wire       step_req_i,
    input  wire       dbus_ren_i,
    input  wire [1:0] dbus_addr_i,
    output reg  [7:0] dbus_rdata_o,
    output reg        halted_o,
    output reg        fetch_o
);

    // Control FSM states
    localparam [1:0] RUN     = 2'd0,
                     HALTING = 2'd1,
                     HALTED  = 2'd2,
                     STEP    = 2'd3;

    reg [1:0] state;

    always @(posedge clk) begin
        if (rst) begin
            state        <= RUN;
            fetch_o      <= 1'b0;
            halted_o     <= 1'b0;
            dbus_rdata_o <= 8'b0;
        end else begin
            // Debug-bus read: load on the edge ren is sampled high,
            // present one cycle later, and hold while ren is low.
            if (dbus_ren_i) begin
                case (dbus_addr_i)
                    2'd0: dbus_rdata_o <= 8'h5A;
                    2'd1: dbus_rdata_o <= 8'hC3;
                    2'd2: dbus_rdata_o <= 8'h0F;
                    2'd3: dbus_rdata_o <= 8'h96;
                endcase
            end

            // Run/halt/step/resume control
            case (state)
                RUN: begin
                    if (halt_req_i) begin
                        // fetch stays high through the next edge (E+1)
                        state    <= HALTING;
                        fetch_o  <= 1'b1;
                        halted_o <= 1'b0;
                    end else begin
                        state    <= RUN;
                        fetch_o  <= 1'b1;
                        halted_o <= 1'b0;
                    end
                end

                HALTING: begin
                    // fetch goes low, halted first asserts (E+2)
                    state    <= HALTED;
                    fetch_o  <= 1'b0;
                    halted_o <= 1'b1;
                end

                HALTED: begin
                    if (resume_req_i) begin
                        state    <= RUN;
                        fetch_o  <= 1'b1;
                        halted_o <= 1'b0;
                    end else if (step_req_i && !halt_req_i) begin
                        // single fetch pulse next cycle
                        state    <= STEP;
                        fetch_o  <= 1'b1;
                        halted_o <= 1'b0;
                    end else begin
                        // includes halt_req & step_req both high: stay halted
                        state    <= HALTED;
                        fetch_o  <= 1'b0;
                        halted_o <= 1'b1;
                    end
                end

                STEP: begin
                    // return to halted after the single fetch cycle
                    state    <= HALTED;
                    fetch_o  <= 1'b0;
                    halted_o <= 1'b1;
                end

                default: begin
                    state    <= RUN;
                    fetch_o  <= 1'b1;
                    halted_o <= 1'b0;
                end
            endcase
        end
    end

endmodule