stream-frame-hold

module TopModule (
    input  wire        clk,
    input  wire        rst,
    input  wire        wr_i,
    input  wire [31:0] wr_data,
    input  wire        wr_last_i,
    output wire        wr_ready_o,
    output reg         m_tvalid_o,
    output reg  [31:0] m_tdata_o,
    output reg         m_tlast_o,
    input  wire        m_tready_i
);

    // Depth-8 FIFO storage (data + last flag).
    reg [31:0] mem      [0:7];
    reg        mem_last [0:7];
    reg [2:0]  wr_ptr;
    reg [2:0]  rd_ptr;
    reg [3:0]  count;

    // Stream loader mode: what the next loaded beat is.
    localparam [1:0] NORMAL = 2'd0; // pop payload from FIFO
    localparam [1:0] PAD1   = 2'd1; // first pad beat
    localparam [1:0] PAD2   = 2'd2; // second pad beat (tlast=1)
    reg [1:0]  mode;
    reg [31:0] last_payload;

    // Ready when FIFO is not full.
    assign wr_ready_o = (count < 4'd8);

    wire push = wr_i && wr_ready_o;

    // A beat can be loaded only when valid is already low.
    wire normal_avail   = (count != 4'd0);
    wire beat_available = (mode == NORMAL) ? normal_avail : 1'b1;
    wire can_load       = (~m_tvalid_o) && beat_available;
    wire fifo_pop       = can_load && (mode == NORMAL);

    wire [31:0] pad_data = last_payload ^ 32'h0BADF00D;

    // Data/last for the beat that would be loaded this edge.
    reg [31:0] load_data;
    reg        load_last;
    always @* begin
        case (mode)
            NORMAL:  begin load_data = mem[rd_ptr]; load_last = 1'b0; end
            PAD1:    begin load_data = pad_data;    load_last = 1'b0; end
            default: begin load_data = pad_data;    load_last = 1'b1; end // PAD2
        endcase
    end

    always @(posedge clk) begin
        if (rst) begin
            wr_ptr       <= 3'd0;
            rd_ptr       <= 3'd0;
            count        <= 4'd0;
            mode         <= NORMAL;
            last_payload <= 32'd0;
            m_tvalid_o   <= 1'b0;
            m_tdata_o    <= 32'd0;
            m_tlast_o    <= 1'b0;
        end else begin
            // FIFO push.
            if (push) begin
                mem[wr_ptr]      <= wr_data;
                mem_last[wr_ptr] <= wr_last_i;
                wr_ptr           <= wr_ptr + 3'd1;
            end
            // FIFO pop (only when loading a payload onto the stream).
            if (fifo_pop) begin
                rd_ptr <= rd_ptr + 3'd1;
            end
            // Occupancy updated once for both push and pop, so a beat
            // pushed on the same edge as a load is never lost.
            count <= count + (push ? 4'd1 : 4'd0) - (fifo_pop ? 4'd1 : 4'd0);

            // Registered AXI-Stream output with one idle cycle discipline.
            if (m_tvalid_o && m_tready_i) begin
                // xfer edge: deassert valid, hold data/last.
                m_tvalid_o <= 1'b0;
            end else if (can_load) begin
                // valid already low and a beat is available: load and assert.
                m_tvalid_o <= 1'b1;
                m_tdata_o  <= load_data;
                m_tlast_o  <= load_last;
                case (mode)
                    NORMAL: begin
                        if (mem_last[rd_ptr]) begin
                            last_payload <= mem[rd_ptr];
                            mode         <= PAD1;
                        end else begin
                            mode <= NORMAL;
                        end
                    end
                    PAD1:    mode <= PAD2;
                    default: mode <= NORMAL; // PAD2 -> resume FIFO
                endcase
            end
            // Otherwise (valid high, tready low): hold beat unchanged.
        end
    end

endmodule