coprocessor-dispatcher-classmix

module TopModule (
    input             clk,
    input             rst,
    input             op_valid_i,
    input      [1:0]  op_class_i,
    input      [1:0]  op_rd_i,
    input      [15:0] op_data_i,
    input             c2_done_i,
    output            op_accept_o,
    output reg        wb_valid_o,
    output reg [1:0]  wb_rd_o,
    output reg [15:0] wb_data_o,
    output            c2_busy_o,
    output reg [3:0]  inflight_o
);

    // Per-class slots (class 0 never needs to persist: it is highest priority
    // and always writes back exactly one cycle after accept).
    reg        s1_val;
    reg [1:0]  s1_rd;
    reg [15:0] s1_data;

    reg        s2_val;
    reg [1:0]  s2_rd;
    reg [15:0] s2_data;
    reg        s2_ready;   // sticky: set when c2_done seen while busy

    // ---------------- Combinational accept ----------------
    wire dst_free = ~inflight_o[op_rd_i];
    wire slot_empty =
          (op_class_i == 2'd0) ? 1'b1   :
          (op_class_i == 2'd1) ? ~s1_val :
          (op_class_i == 2'd2) ? ~s2_val : 1'b0;   // class 3 -> never

    assign op_accept_o = op_valid_i & (op_class_i != 2'd3) & dst_free & slot_empty;

    // c2 busy while its slot is occupied (incl. the cycle before writeback edge)
    assign c2_busy_o = s2_val;

    // ---------------- Writeback selection (this cycle -> pulse next cycle) ----
    wire e0 = op_accept_o & (op_class_i == 2'd0);
    wire e1 = s1_val;      // eligible one cycle after becoming valid
    wire e2 = s2_ready;

    wire sel0 = e0;
    wire sel1 = ~e0 & e1;
    wire sel2 = ~e0 & ~e1 & e2;

    // ---------------- Sequential ----------------
    always @(posedge clk) begin
        if (rst) begin
            s1_val   <= 1'b0;
            s1_rd    <= 2'd0;
            s1_data  <= 16'd0;
            s2_val   <= 1'b0;
            s2_rd    <= 2'd0;
            s2_data  <= 16'd0;
            s2_ready <= 1'b0;
            inflight_o <= 4'd0;
            wb_valid_o <= 1'b0;
            wb_rd_o    <= 2'd0;
            wb_data_o  <= 16'd0;
        end else begin
            wb_valid_o <= 1'b0;   // default: pulse for one cycle only

            // ---- accept / store ----
            if (op_accept_o) begin
                inflight_o[op_rd_i] <= 1'b1;
                if (op_class_i == 2'd1) begin
                    s1_val  <= 1'b1;
                    s1_rd   <= op_rd_i;
                    s1_data <= op_data_i << 1;           // *2
                end else if (op_class_i == 2'd2) begin
                    s2_val   <= 1'b1;
                    s2_rd    <= op_rd_i;
                    s2_data  <= op_data_i ^ 16'hffff;
                    s2_ready <= 1'b0;
                end
            end

            // ---- class 2 done -> sticky ready (only while already busy) ----
            if (s2_val & c2_done_i)
                s2_ready <= 1'b1;

            // ---- writeback: at most one per cycle, priority 0 > 1 > 2 ----
            if (sel0) begin
                wb_valid_o <= 1'b1;
                wb_rd_o    <= op_rd_i;
                wb_data_o  <= op_data_i + 16'd1;
                inflight_o[op_rd_i] <= 1'b0;
            end else if (sel1) begin
                wb_valid_o <= 1'b1;
                wb_rd_o    <= s1_rd;
                wb_data_o  <= s1_data;
                s1_val     <= 1'b0;
                inflight_o[s1_rd] <= 1'b0;
            end else if (sel2) begin
                wb_valid_o <= 1'b1;
                wb_rd_o    <= s2_rd;
                wb_data_o  <= s2_data;
                s2_val     <= 1'b0;
                s2_ready   <= 1'b0;
                inflight_o[s2_rd] <= 1'b0;
            end
        end
    end

endmodule