bus-slave-abort-ack

module TopModule(
  input  wire        clk,
  input  wire        rst,
  input  wire        cyc_i,
  input  wire        stb_i,
  input  wire        we_i,
  input  wire [1:0]  adr_i,
  input  wire [15:0] dat_i,
  output reg         stall_o,
  output reg         ack_o,
  output reg [15:0]  dat_o
);

  // Four 16-bit slots plus their primed bits
  reg [15:0] slots [0:3];
  reg [3:0]  primed;

  // Pipeline: a request accepted at E advances one stage per posedge.
  // A read responds when it is in stage 2 (edge E+2).
  // A write commits/responds when it is in stage 3 (edge E+3).
  reg        s1_v, s1_wr;
  reg [1:0]  s1_adr;
  reg [15:0] s1_dat;
  reg [15:0] s1_cap;
  reg        s1_prm;

  reg        s2_v, s2_wr;
  reg [1:0]  s2_adr;
  reg [15:0] s2_dat;
  reg [15:0] s2_cap;
  reg        s2_prm;

  reg        s3_v, s3_wr;
  reg [1:0]  s3_adr;
  reg [15:0] s3_dat;

  integer    i;

  reg        rfire, wfire;
  reg [15:0] rdata, wdata;

  // mix(a,x): into lane k pack the bit-reversed source lane (k+a) mod 4.
  // Lane j in increasing bit order = { x[j], x[j+4], x[j+8], x[j+12] }.
  function [15:0] mix;
    input [1:0]  a;
    input [15:0] x;
    integer k;
    integer s;
    begin
      mix = 16'b0;
      for (k = 0; k < 4; k = k + 1) begin
        s = (k + a) & 3;
        mix[k]      = x[s+12];
        mix[k+4]    = x[s+8];
        mix[k+8]    = x[s+4];
        mix[k+12]   = x[s];
      end
    end
  endfunction

  always @(posedge clk) begin
    if (rst) begin
      for (i = 0; i < 4; i = i + 1)
        slots[i] <= 16'b0;
      primed  <= 4'b0;
      s1_v <= 1'b0; s2_v <= 1'b0; s3_v <= 1'b0;
      s1_wr <= 1'b0; s2_wr <= 1'b0; s3_wr <= 1'b0;
      s1_adr <= 2'b0; s2_adr <= 2'b0; s3_adr <= 2'b0;
      s1_dat <= 16'b0; s2_dat <= 16'b0; s3_dat <= 16'b0;
      s1_cap <= 16'b0; s2_cap <= 16'b0;
      s1_prm <= 1'b0; s2_prm <= 1'b0;
      stall_o <= 1'b0;
      ack_o   <= 1'b0;
      dat_o   <= 16'b0;
    end else begin
      // Advance the pipeline (RHS use pre-edge values).
      s2_v   <= s1_v;   s2_wr  <= s1_wr;  s2_adr <= s1_adr;
      s2_dat <= s1_dat; s2_cap <= s1_cap; s2_prm <= s1_prm;
      s3_v   <= s2_v;   s3_wr  <= s2_wr;  s3_adr <= s2_adr; s3_dat <= s2_dat;

      // New acceptance into stage 1 (default: empty).
      s1_v <= 1'b0;
      if (cyc_i && stb_i && !stall_o) begin
        s1_v   <= 1'b1;
        s1_wr  <= we_i;
        s1_adr <= adr_i;
        s1_dat <= dat_i;
        s1_cap <= slots[adr_i];
        s1_prm <= primed[adr_i];
      end

      // Registered stall: an accepted write raises stall after E+1 and E+2.
      // A write currently in stage 1 or 2 will occupy stage 2 or 3 next cycle.
      stall_o <= (s1_v & s1_wr) | (s2_v & s2_wr);

      // Response events at this edge.
      rfire = s2_v & ~s2_wr;
      wfire = s3_v &  s3_wr;
      rdata = s2_prm ? mix(s2_adr, s2_cap) : 16'b0;
      wdata = mix(s3_adr, slots[s3_adr]) ^ s3_dat;

      // Write commit is unconditional on cyc_i (dropped writes still commit).
      if (wfire) begin
        slots[s3_adr]  <= wdata;
        primed[s3_adr] <= 1'b1;
      end

      // Registered outputs: read data wins on a shared edge; ack gated by cyc_i.
      if ((rfire | wfire) & cyc_i) begin
        ack_o <= 1'b1;
        dat_o <= rfire ? rdata : wdata;
      end else begin
        ack_o <= 1'b0;
        dat_o <= 16'b0;
      end
    end
  end

endmodule