debug-halt-step-fsm

// Control block: stops/resumes a core over a debug port.
//
// Timing convention (fixed by the dbus spec): an input sampled at edge X
// produces its registered result on the wire during the following cycle,
// which the spec refers to as the value "at edge X+1".
//
// State machine (registered outputs):
//   RUNNING : fetch=1, halted=0
//   HALTING : fetch=1, halted=0  (one transitional cycle after a halt req)
//   HALTED  : fetch=0, halted=1
//   STEP    : fetch=1, halted=0  (one-cycle fetch pulse out of HALTED)
//
// dbus read is an independent single-register read, active in any state.

module TopModule (
    input  logic       clk,
    input  logic       rst,
    input  logic       halt_req_i,
    input  logic       resume_req_i,
    input  logic       step_req_i,
    input  logic       dbus_ren_i,
    input  logic [1:0] dbus_addr_i,
    output logic [7:0] dbus_rdata_o,
    output logic       halted_o,
    output logic       fetch_o
);

    localparam logic [1:0] RUNNING = 2'd0;
    localparam logic [1:0] HALTING = 2'd1;
    localparam logic [1:0] HALTED  = 2'd2;
    localparam logic [1:0] STEP    = 2'd3;

    logic [1:0] state_q;
    logic [1:0] next_state;

    // Next-state logic
    always_comb begin
        case (state_q)
            RUNNING: next_state = halt_req_i ? HALTING : RUNNING;
            HALTING: next_state = HALTED;
            HALTED:  begin
                if      (halt_req_i)   next_state = HALTED;   // halt dominates (incl. halt+step)
                else if (resume_req_i) next_state = RUNNING;
                else if (step_req_i)   next_state = STEP;
                else                   next_state = HALTED;
            end
            STEP:    next_state = HALTED;
            default: next_state = RUNNING;
        endcase
    end

    // Registered state, registered outputs, registered dbus read.
    always_ff @(posedge clk) begin
        if (rst) begin
            state_q      <= RUNNING;
            fetch_o      <= 1'b0;
            halted_o     <= 1'b0;
            dbus_rdata_o <= 8'b0;
        end else begin
            state_q  <= next_state;
            fetch_o  <= (next_state != HALTED);
            halted_o <= (next_state == HALTED);

            if (dbus_ren_i) begin
                case (dbus_addr_i)
                    2'd0:    dbus_rdata_o <= 8'h5A;
                    2'd1:    dbus_rdata_o <= 8'hC3;
                    2'd2:    dbus_rdata_o <= 8'h0F;
                    default: dbus_rdata_o <= 8'h96;
                endcase
            end
            // else: hold previous data while dbus_ren_i is low
        end
    end

endmodule