Design a SystemVerilog module named TopModule that splits a stream of message bytes across four parallel lanes, pads each lane independently, and frames the result into 64-bit blocks, with valid/ready handshakes on both the byte input and the block output.
Ports, one bit each unless noted: inputs clk, rst, start_i, byte_i [7:0], byte_valid_i, last_i, block_ready_i; outputs block_o [63:0], block_valid_o, byte_ready_o, done_o, busy_o. All five outputs are registered. rst is synchronous active high: every output clears to 0 except byte_ready_o which clears to 1. block_o is compared only while block_valid_o is high.
A byte is accepted on a rising edge where byte_valid_i and byte_ready_o are both high. start_i accompanies the first accepted byte, last_i the final one. The message length is its accepted-byte count, 1 to 8191.
Number the accepted bytes from zero in arrival order. Byte k belongs to lane k mod 4. Within a lane the bytes keep their arrival order and pack eight per block, big-endian, the earliest byte in block_o[63:56].
Each lane is padded on its own byte stream. Append 0x80 in the byte position immediately after that lane's last byte, fill the rest with zero, and place that lane's length in bits, which is eight times the number of bytes routed to the lane, as a 16-bit big-endian value in byte6 and byte7 of the lane's final block. Emit the fewest blocks per lane that hold the lane's bytes, the marker, the fill and the length. When a lane's byte count is a multiple of eight, its 0x80 and length occupy one additional all-padding block. When the block holding a lane's last byte has six or seven byte positions filled, the length does not share it: that block carries the bytes, 0x80 and zero fill, and a following block holds only the length. A lane with no bytes still emits one block holding 0x80, zero fill and a zero length.
Index the blocks of each lane from zero. Emit all four lanes' block 0, then all four lanes' block 1, and so on; within an index emit lane 0 first through lane 3. Skip a lane at indices beyond its block count. block_valid_o is high while a block is presented and a block is accepted on a rising edge where block_valid_o and block_ready_i are both high; while it is stalled block_o and block_valid_o hold. Present one block at a time.
byte_ready_o is high while bytes are accepted and low while blocks are leaving. busy_o is high from the first accepted byte until the final block is accepted, low otherwise. The final block is the highest index reached by any lane, taken in the highest-numbered lane that reaches it. done_o is high for the cycles that block is presented, so on its accepting edge block_valid_o, block_ready_i and done_o are all high.
Put the implementation in /app/dut.sv with the module named TopModule and exactly this port list. It is compiled with iverilog -g2012 against a held-back reference and simulated under randomized stimulus that drives the byte side and randomly stalls the block side; the design must match the reference on every output on every clock edge for every sample. Use plain synthesizable SystemVerilog: module/endmodule, always/assign, localparam, reg, wire, logic and functions. Do not use preprocessor directives (include, define, ifdef, ifndef, undef, the token-paste operator), do not call simulator system tasks ($display, $write, $finish, $stop, $system, $fopen, $fwrite, $fdisplay, $fread, $fgets, $feof, $readmem, $writemem, $dumpfile, $dumpvars, $fatal, $exit, $error, $warning, $assert), do not use force or release, and do not import DPI-C; the verifier rejects the submission before simulation if any of these appear in /app/dut.sv.