tests/test.sh exit code (0 → resolved); the classification below is post-hoc and cannot change it.// UART-style receiver
// Synthesizable single-clock implementation.
module TopModule(
input clk,
input reset,
input in,
input [15:0] baud_div_i,
input [2:0] frame_fmt_i,
input clear_err_i,
input data_ack_i,
output reg [7:0] out_byte,
output reg done,
output reg parity_err_o,
output reg frame_err_o,
output reg break_o,
output reg ovf_o,
output reg [7:0] byte_count_o
);
// ---- states ----
localparam S_IDLE = 3'd0;
localparam S_START = 3'd1;
localparam S_DATA = 3'd2;
localparam S_PAR = 3'd3;
localparam S_STOP = 3'd4;
reg [2:0] state;
// latched frame parameters
reg [15:0] baud_lat; // >=1
reg [3:0] ndata_lat; // 7 or 8
reg has_par_lat;
reg par_odd_lat; // 0=even,1=odd
reg mask7_lat; // force bit7=0
reg [1:0] nstop_lat; // 1 or 2
// frame progress
reg [19:0] sub_cnt; // clock within current bit
reg [3:0] bit_idx;
reg [1:0] stop_idx;
reg [7:0] rx_data;
reg par_bad;
reg stop_bad;
// edge detect / break detect
reg in_r;
reg [31:0] low_cnt;
// per-bit timing
wire [19:0] bit_ticks = {baud_lat, 4'b0000}; // 16*baud
wire [19:0] mid = {1'b0, baud_lat, 3'b000}; // 8*baud
// break threshold: 11*16*baud = 176*baud (live baud)
wire [31:0] brk_thr = 32'd176 * baud_div_i;
// combinational scratch (blocking within always)
reg set_par, set_frame, set_ovf, commit;
always @(posedge clk) begin
if (reset) begin
state <= S_IDLE;
out_byte <= 8'd0;
done <= 1'b0;
parity_err_o <= 1'b0;
frame_err_o <= 1'b0;
break_o <= 1'b0;
ovf_o <= 1'b0;
byte_count_o <= 8'd0;
baud_lat <= 16'd1;
ndata_lat <= 4'd8;
has_par_lat <= 1'b0;
par_odd_lat <= 1'b0;
mask7_lat <= 1'b0;
nstop_lat <= 2'd1;
sub_cnt <= 20'd0;
bit_idx <= 4'd0;
stop_idx <= 2'd0;
rx_data <= 8'd0;
par_bad <= 1'b0;
stop_bad <= 1'b0;
in_r <= in;
low_cnt <= 32'd0;
end else begin
in_r = in; // track line for edge detect (updated below via NBA)
set_par = 1'b0;
set_frame = 1'b0;
set_ovf = 1'b0;
commit = 1'b0;
// use registered previous value for edge detection
// (in_r reg holds previous cycle's value; assign new below)
case (state)
// ------------------------------------------------------
S_IDLE: begin
if (in_r_prev && !in) begin
// latch baud (0 -> 1)
baud_lat <= (baud_div_i == 16'd0) ? 16'd1 : baud_div_i;
// decode format
case (frame_fmt_i)
3'b001: begin ndata_lat<=4'd7; has_par_lat<=1'b0; par_odd_lat<=1'b0; nstop_lat<=2'd1; mask7_lat<=1'b1; end
3'b010: begin ndata_lat<=4'd8; has_par_lat<=1'b1; par_odd_lat<=1'b0; nstop_lat<=2'd1; mask7_lat<=1'b0; end
3'b011: begin ndata_lat<=4'd8; has_par_lat<=1'b1; par_odd_lat<=1'b1; nstop_lat<=2'd1; mask7_lat<=1'b0; end
3'b100: begin ndata_lat<=4'd8; has_par_lat<=1'b0; par_odd_lat<=1'b0; nstop_lat<=2'd2; mask7_lat<=1'b0; end
default:begin ndata_lat<=4'd8; has_par_lat<=1'b0; par_odd_lat<=1'b0; nstop_lat<=2'd1; mask7_lat<=1'b0; end
endcase
state <= S_START;
sub_cnt <= 20'd0;
bit_idx <= 4'd0;
stop_idx <= 2'd0;
rx_data <= 8'd0;
par_bad <= 1'b0;
stop_bad <= 1'b0;
end
end
// ------------------------------------------------------
S_START: begin
if (sub_cnt == mid) begin
if (in) begin
// high at start midpoint -> abort, no flags
state <= S_IDLE;
end
end
if (sub_cnt == bit_ticks - 20'd1) begin
sub_cnt <= 20'd0;
state <= S_DATA;
bit_idx <= 4'd0;
end else begin
sub_cnt <= sub_cnt + 20'd1;
end
end
// ------------------------------------------------------
S_DATA: begin
if (sub_cnt == mid) begin
rx_data[bit_idx] <= in;
end
if (sub_cnt == bit_ticks - 20'd1) begin
sub_cnt <= 20'd0;
if (bit_idx == ndata_lat - 4'd1) begin
if (has_par_lat) begin
state <= S_PAR;
end else begin
state <= S_STOP;
stop_idx <= 2'd0;
end
end else begin
bit_idx <= bit_idx + 4'd1;
end
end else begin
sub_cnt <= sub_cnt + 20'd1;
end
end
// ------------------------------------------------------
S_PAR: begin
if (sub_cnt == mid) begin
if ((^rx_data ^ in) != par_odd_lat) begin
par_bad <= 1'b1;
set_par = 1'b1;
end
end
if (sub_cnt == bit_ticks - 20'd1) begin
sub_cnt <= 20'd0;
state <= S_STOP;
stop_idx <= 2'd0;
end else begin
sub_cnt <= sub_cnt + 20'd1;
end
end
// ------------------------------------------------------
S_STOP: begin
if (sub_cnt == mid) begin
if (!in) begin
stop_bad <= 1'b1;
set_frame = 1'b1;
end
end
if (sub_cnt == bit_ticks - 20'd1) begin
sub_cnt <= 20'd0;
if (stop_idx == nstop_lat - 2'd1) begin
state <= S_IDLE;
if (!par_bad && !stop_bad) begin
commit = 1'b1;
end
end else begin
stop_idx <= stop_idx + 2'd1;
end
end else begin
sub_cnt <= sub_cnt + 20'd1;
end
end
// ------------------------------------------------------
default: state <= S_IDLE;
endcase
// ---- commit / done / overflow ----
if (commit) begin
out_byte <= mask7_lat ? {1'b0, rx_data[6:0]} : rx_data;
byte_count_o <= (byte_count_o == 8'hFF) ? 8'hFF : (byte_count_o + 8'd1);
done <= 1'b1;
if (done && !data_ack_i) set_ovf = 1'b1;
end else begin
if (data_ack_i) done <= 1'b0;
end
// ---- sticky flags (same-cycle set wins over clear) ----
if (set_par) parity_err_o <= 1'b1;
else if (clear_err_i) parity_err_o <= 1'b0;
if (set_frame) frame_err_o <= 1'b1;
else if (clear_err_i) frame_err_o <= 1'b0;
if (set_ovf) ovf_o <= 1'b1;
else if (clear_err_i) ovf_o <= 1'b0;
// ---- break detection (live baud) ----
if (in) begin
low_cnt <= 32'd0;
break_o <= 1'b0; // deassert one clock after high
end else begin
if (!(&low_cnt)) low_cnt <= low_cnt + 32'd1;
if ((baud_div_i != 16'd0) && ((low_cnt + 32'd1) >= brk_thr))
break_o <= 1'b1;
end
// update edge-detect register
in_r <= in;
end
end
// previous registered line value for edge detection
// (declared as separate reg so the always block reads last cycle's value)
reg in_r_prev;
always @(posedge clk) begin
if (reset) in_r_prev <= in;
else in_r_prev <= in;
end
endmodule
// UART-style receiver
// Synthesizable single-clock implementation.
module TopModule(
input clk,
input reset,
input in,
input [15:0] baud_div_i,
input [2:0] frame_fmt_i,
input clear_err_i,
input data_ack_i,
output reg [7:0] out_byte,
output reg done,
output reg parity_err_o,
output reg frame_err_o,
output reg break_o,
output reg ovf_o,
output reg [7:0] byte_count_o
);
// ---- states ----
localparam S_IDLE = 3'd0;
localparam S_START = 3'd1;
localparam S_DATA = 3'd2;
localparam S_PAR = 3'd3;
localparam S_STOP = 3'd4;
reg [2:0] state;
// latched frame parameters
reg [15:0] baud_lat; // >=1
reg [3:0] ndata_lat; // 7 or 8
reg has_par_lat;
reg par_odd_lat; // 0=even,1=odd
reg mask7_lat; // force bit7=0
reg [1:0] nstop_lat; // 1 or 2
// frame progress
reg [19:0] sub_cnt; // clock within current bit
reg [3:0] bit_idx;
reg [1:0] stop_idx;
reg [7:0] rx_data;
reg par_bad;
reg stop_bad;
// edge detect / break detect
reg in_r; // previous-cycle line value
reg [31:0] low_cnt;
// per-bit timing
wire [19:0] bit_ticks = {baud_lat, 4'b0000}; // 16*baud
wire [19:0] mid = {1'b0, baud_lat, 3'b000}; // 8*baud
// break threshold: 11*16*baud = 176*baud (live baud)
wire [31:0] brk_thr = 32'd176 * baud_div_i;
// combinational scratch (blocking within always)
reg set_par, set_frame, set_ovf, commit;
always @(posedge clk) begin
if (reset) begin
state <= S_IDLE;
out_byte <= 8'd0;
done <= 1'b0;
parity_err_o <= 1'b0;
frame_err_o <= 1'b0;
break_o <= 1'b0;
ovf_o <= 1'b0;
byte_count_o <= 8'd0;
baud_lat <= 16'd1;
ndata_lat <= 4'd8;
has_par_lat <= 1'b0;
par_odd_lat <= 1'b0;
mask7_lat <= 1'b0;
nstop_lat <= 2'd1;
sub_cnt <= 20'd0;
bit_idx <= 4'd0;
stop_idx <= 2'd0;
rx_data <= 8'd0;
par_bad <= 1'b0;
stop_bad <= 1'b0;
in_r <= in;
low_cnt <= 32'd0;
end else begin
set_par = 1'b0;
set_frame = 1'b0;
set_ovf = 1'b0;
commit = 1'b0;
case (state)
// ------------------------------------------------------
S_IDLE: begin
// idle high-to-low transition starts a frame
if (in_r && !in) begin
baud_lat <= (baud_div_i == 16'd0) ? 16'd1 : baud_div_i;
case (frame_fmt_i)
3'b001: begin ndata_lat<=4'd7; has_par_lat<=1'b0; par_odd_lat<=1'b0; nstop_lat<=2'd1; mask7_lat<=1'b1; end
3'b010: begin ndata_lat<=4'd8; has_par_lat<=1'b1; par_odd_lat<=1'b0; nstop_lat<=2'd1; mask7_lat<=1'b0; end
3'b011: begin ndata_lat<=4'd8; has_par_lat<=1'b1; par_odd_lat<=1'b1; nstop_lat<=2'd1; mask7_lat<=1'b0; end
3'b100: begin ndata_lat<=4'd8; has_par_lat<=1'b0; par_odd_lat<=1'b0; nstop_lat<=2'd2; mask7_lat<=1'b0; end
default:begin ndata_lat<=4'd8; has_par_lat<=1'b0; par_odd_lat<=1'b0; nstop_lat<=2'd1; mask7_lat<=1'b0; end
endcase
state <= S_START;
sub_cnt <= 20'd0;
bit_idx <= 4'd0;
stop_idx <= 2'd0;
rx_data <= 8'd0;
par_bad <= 1'b0;
stop_bad <= 1'b0;
end
end
// ------------------------------------------------------
S_START: begin
if (sub_cnt == mid) begin
if (in) begin
// high at start midpoint -> abort, no flags
state <= S_IDLE;
end
end
if (sub_cnt == bit_ticks - 20'd1) begin
sub_cnt <= 20'd0;
state <= S_DATA;
bit_idx <= 4'd0;
end else begin
sub_cnt <= sub_cnt + 20'd1;
end
end
// ------------------------------------------------------
S_DATA: begin
if (sub_cnt == mid) begin
rx_data[bit_idx] <= in;
end
if (sub_cnt == bit_ticks - 20'd1) begin
sub_cnt <= 20'd0;
if (bit_idx == ndata_lat - 4'd1) begin
if (has_par_lat) begin
state <= S_PAR;
end else begin
state <= S_STOP;
stop_idx <= 2'd0;
end
end else begin
bit_idx <= bit_idx + 4'd1;
end
end else begin
sub_cnt <= sub_cnt + 20'd1;
end
end
// ------------------------------------------------------
S_PAR: begin
if (sub_cnt == mid) begin
// even: xor(data,parity)=0 ; odd: =1
if ((^rx_data ^ in) != par_odd_lat) begin
par_bad <= 1'b1;
set_par = 1'b1;
end
end
if (sub_cnt == bit_ticks - 20'd1) begin
sub_cnt <= 20'd0;
state <= S_STOP;
stop_idx <= 2'd0;
end else begin
sub_cnt <= sub_cnt + 20'd1;
end
end
// ------------------------------------------------------
S_STOP: begin
if (sub_cnt == mid) begin
if (!in) begin
stop_bad <= 1'b1;
set_frame = 1'b1;
end
end
if (sub_cnt == bit_ticks - 20'd1) begin
sub_cnt <= 20'd0;
if (stop_idx == nstop_lat - 2'd1) begin
state <= S_IDLE;
if (!par_bad && !stop_bad) begin
commit = 1'b1;
end
end else begin
stop_idx <= stop_idx + 2'd1;
end
end else begin
sub_cnt <= sub_cnt + 20'd1;
end
end
// ------------------------------------------------------
default: state <= S_IDLE;
endcase
// ---- commit / done / overflow ----
if (commit) begin
out_byte <= mask7_lat ? {1'b0, rx_data[6:0]} : rx_data;
byte_count_o <= (byte_count_o == 8'hFF) ? 8'hFF : (byte_count_o + 8'd1);
done <= 1'b1; // new done set; ack cannot clear it this cycle
if (done && !data_ack_i) set_ovf = 1'b1; // old done still high, unacked -> overflow
end else begin
if (data_ack_i) done <= 1'b0;
end
// ---- sticky flags (same-cycle set wins over clear) ----
if (set_par) parity_err_o <= 1'b1;
else if (clear_err_i) parity_err_o <= 1'b0;
if (set_frame) frame_err_o <= 1'b1;
else if (clear_err_i) frame_err_o <= 1'b0;
if (set_ovf) ovf_o <= 1'b1;
else if (clear_err_i) ovf_o <= 1'b0;
// ---- break detection (live baud) ----
if (in) begin
low_cnt <= 32'd0;
break_o <= 1'b0; // deassert one clock after high
end else begin
if (!(&low_cnt)) low_cnt <= low_cnt + 32'd1;
if ((baud_div_i != 16'd0) && ((low_cnt + 32'd1) >= brk_thr))
break_o <= 1'b1;
end
// ---- edge-detect register update ----
in_r <= in;
end
end
endmodule
(iverilog -g2012 -o /tmp/dut.out dut.sv 2>&1 && echo "IVERILOG OK") || (verilator --lint-only -Wno-lint dut.sv 2>&1 && echo "VERILATOR OK") || echo "no simulator available"
IVERILOG OK [stdout] IVERILOG OK
module tb;
reg clk=0, reset=1, in=1;
reg [15:0] baud=1;
reg [2:0] fmt=0;
reg clr=0, ack=0;
wire [7:0] ob; wire done, pe, fe, brk, ovf; wire [7:0] cnt;
TopModule d(clk,reset,in,baud,fmt,clr,ack,ob,done,pe,fe,brk,ovf,cnt);
always #5 clk=~clk;
integer i;
// send one bit value 'b' over 16 clocks (baud=1)
task send_bit(input b);
integer k;
begin
in=b;
for(k=0;k<16;k=k+1) @(posedge clk);
end
endtask
reg [7:0] data;
task send_byte8n1(input [7:0] db);
integer k;
begin
send_bit(0); // start
for(k=0;k<8;k=k+1) send_bit(db[k]); // lsb first
send_bit(1); // stop
end
endtask
initial begin
@(posedge clk); @(posedge clk); reset=0; in=1;
repeat(4) @(posedge clk);
send_byte8n1(8'h55);
// wait a bit for commit
repeat(4) @(posedge clk);
$display("after 0x55: out=%h done=%b cnt=%d pe=%b fe=%b ovf=%b", ob,done,cnt,pe,fe,ovf);
if(ob!==8'h55 || done!==1 || cnt!==8'd1) $display("FAIL frame1");
// ack clears done
ack=1; @(posedge clk); ack=0; @(posedge clk);
$display("after ack: done=%b", done);
if(done!==0) $display("FAIL ack");
// send a frame with bad stop (stop=0) -> frame_err, no commit
send_bit(0);
for(i=0;i<8;i=i+1) send_bit(8'hA3[i]);
send_bit(0); // bad stop
send_bit(1); // return line high
repeat(4) @(posedge clk);
$display("bad stop: out=%h done=%b cnt=%d fe=%b", ob,done,cnt,fe);
if(fe!==1 || cnt!==8'd1) $display("FAIL framerr");
clr=1; @(posedge clk); clr=0; @(posedge clk);
$display("after clr: fe=%b", fe);
if(fe!==0) $display("FAIL clr");
$display("DONE");
$finish;
end
endmodule
cd /tmp && iverilog -g2012 -o t.out /app/dut.sv tb.sv 2>&1 && vvp t.out 2>&1
Exit code 2 tb.sv:45: syntax error tb.sv:45: error: Syntax error in task arguments. [error] tool reported failure
/tmp/tb.sv
// send a frame with bad stop (stop=0) -> frame_err, no commit
send_bit(0);
for(i=0;i<8;i=i+1) send_bit(8'hA3[i]); // send a frame with bad stop (stop=0) -> frame_err, no commit
data=8'hA3;
send_bit(0);
for(i=0;i<8;i=i+1) send_bit(data[i]);cd /tmp && iverilog -g2012 -o t.out /app/dut.sv tb.sv 2>&1 && vvp t.out 2>&1
after 0x55: out=55 done=1 cnt= 1 pe=0 fe=0 ovf=0 after ack: done=1 FAIL ack bad stop: out=55 done=1 cnt= 1 fe=1 after clr: fe=1 FAIL clr DONE tb.sv:57: $finish called at 3535 (1s) Shell cwd was reset to /app [stdout] after 0x55: out=55 done=1 cnt= 1 pe=0 fe=0 ovf=0 after ack: done=1 FAIL ack bad stop: out=55 done=1 cnt= 1 fe=1 after clr: fe=1 FAIL clr DONE tb.sv:57: $finish called at 3535 (1s) [stderr] Shell cwd was reset to /app
cd /tmp && cat > tb2.sv <<'EOF'
module tb2;
reg clk=0, reset=1, in=1;
reg [15:0] baud=1; reg [2:0] fmt=0; reg clr=0, ack=0;
wire [7:0] ob; wire done, pe, fe, brk, ovf; wire [7:0] cnt;
TopModule d(clk,reset,in,baud,fmt,clr,ack,ob,done,pe,fe,brk,ovf,cnt);
always #5 clk=~clk;
integer k;
task send_bit(input b); integer j; begin in=b; for(j=0;j<16;j=j+1) @(posedge clk); end endtask
initial begin
@(posedge clk); @(posedge clk); reset=0; in=1; repeat(4) @(posedge clk);
send_bit(0);
send_bit(1);send_bit(0);send_bit(1);send_bit(0);send_bit(1);send_bit(0);send_bit(1);send_bit(0); //0x55
send_bit(1); // stop
repeat(2) @(posedge clk);
$display("t=%0t done=%b ob=%h cnt=%d",$time,done,ob,cnt);
ack=1; @(posedge clk);
$display("t=%0t (ack sampled) done=%b",$time,done);
ack=0; @(posedge clk);
$display("t=%0t done=%b",$time,done);
@(posedge clk);
$display("t=%0t done=%b",$time,done);
$finish;
end
endmodule
EOF
iverilog -g2012 -o t2.out /app/dut.sv tb2.sv 2>&1 && vvp t2.out 2>&1t=1675 done=1 ob=55 cnt= 1 t=1685 (ack sampled) done=1 t=1695 done=1 t=1705 done=1 tb2.sv:22: $finish called at 1705 (1s) Shell cwd was reset to /app [stdout] t=1675 done=1 ob=55 cnt= 1 t=1685 (ack sampled) done=1 t=1695 done=1 t=1705 done=1 tb2.sv:22: $finish called at 1705 (1s) [stderr] Shell cwd was reset to /app
cd /tmp && cp /app/dut.sv dutd.sv
# insert a debug display in the commit/else region
python3 - <<'PY'
s=open('dutd.sv').read()
s=s.replace(" end else begin\n if (data_ack_i) done <= 1'b0;\n end",
" end else begin\n if (data_ack_i) done <= 1'b0;\n if (data_ack_i) $display(\"DBG ack-clear t=%0t state=%0d\",$time,state);\n end")
open('dutd.sv','w').write(s)
print("done" if "DBG" in s else "NOPATCH")
PY
sed -i 's/TopModule d/TopModule d/' tb2.sv
iverilog -g2012 -o t3.out dutd.sv tb2.sv 2>&1 && vvp t3.out 2>&1done t=1675 done=1 ob=55 cnt= 1 t=1685 (ack sampled) done=1 t=1695 done=1 t=1705 done=1 tb2.sv:22: $finish called at 1705 (1s) Shell cwd was reset to /app [stdout] done t=1675 done=1 ob=55 cnt= 1 t=1685 (ack sampled) done=1 t=1695 done=1 t=1705 done=1 tb2.sv:22: $finish called at 1705 (1s) [stderr] Shell cwd was reset to /app
cd /tmp && cp /app/dut.sv dutd.sv
python3 - <<'PY'
s=open('dutd.sv').read()
anchor=" // ---- sticky flags (same-cycle set wins over clear) ----"
dbg=' if($time>1660 && $time<1720) $display("DBG t=%0t commit=%b ack=%b done=%b state=%0d",$time,commit,data_ack_i,done,state);\n'
s=s.replace(anchor, dbg+anchor)
open('dutd.sv','w').write(s)
print("OK" if "DBG t=" in s else "NO")
PY
iverilog -g2012 -o t3.out dutd.sv tb2.sv 2>&1 && vvp t3.out 2>&1OK DBG t=1665 commit=1 ack=0 done=0 state=4 DBG t=1675 commit=0 ack=0 done=1 state=0 t=1675 done=1 ob=55 cnt= 1 t=1685 (ack sampled) done=1 DBG t=1685 commit=0 ack=0 done=1 state=0 DBG t=1695 commit=0 ack=0 done=1 state=0 t=1695 done=1 t=1705 done=1 tb2.sv:22: $finish called at 1705 (1s) Shell cwd was reset to /app [stdout] OK DBG t=1665 commit=1 ack=0 done=0 state=4 DBG t=1675 commit=0 ack=0 done=1 state=0 t=1675 done=1 ob=55 cnt= 1 t=1685 (ack sampled) done=1 DBG t=1685 commit=0 ack=0 done=1 state=0 DBG t=1695 commit=0 ack=0 done=1 state=0 t=1695 done=1 t=1705 done=1 tb2.sv:22: $finish called at 1705 (1s) [stderr] Shell cwd was reset to /app
cd /tmp && cat > tb.sv <<'EOF'
`timescale 1ns/1ps
module tb;
reg clk=0, reset=1, in=1;
reg [15:0] baud=1; reg [2:0] fmt=0; reg clr=0, ack=0;
wire [7:0] ob; wire done, pe, fe, brk, ovf; wire [7:0] cnt;
TopModule d(clk,reset,in,baud,fmt,clr,ack,ob,done,pe,fe,brk,ovf,cnt);
always #5 clk=~clk;
integer fails=0;
task tick; begin @(posedge clk); #1; end endtask
task send_bit(input b); integer j; begin in=b; repeat(16) tick; end endtask
task chk(input cond, input [127:0] name);
begin if(!cond) begin $display("FAIL %0s",name); fails=fails+1; end end
endtask
reg [7:0] data; integer i;
task frame8n1(input [7:0] db, input stopv);
begin send_bit(0); for(i=0;i<8;i=i+1) send_bit(db[i]); send_bit(stopv); end
endtask
initial begin
tick; tick; reset=0; in=1; repeat(4) tick;
// good 8N1 0x55
frame8n1(8'h55,1); repeat(2) tick;
chk(ob===8'h55 && done===1'b1 && cnt===8'd1 && pe===0 && fe===0, "g1_8n1");
// ack clears done
ack=1; tick; ack=0; tick;
chk(done===1'b0, "ack_clear");
// second good frame -> count=2
frame8n1(8'hA5,1); repeat(2) tick;
chk(ob===8'hA5 && done===1'b1 && cnt===8'd2, "g2");
// overflow: commit while done high, ack low -> ovf, replace byte
frame8n1(8'h3C,1); repeat(2) tick;
chk(ob===8'h3C && cnt===8'd3 && ovf===1'b1 && done===1'b1, "ovf");
// clear ovf + drain done
clr=1; ack=1; tick; clr=0; ack=0; tick;
chk(ovf===1'b0 && done===1'b0, "clr_ovf");
// bad stop -> frame_err, no commit, count unchanged (3)
send_bit(0); data=8'h77; for(i=0;i<8;i=i+1) send_bit(data[i]); send_bit(0); send_bit(1);
repeat(2) tick;
chk(fe===1'b1 && cnt===8'd3 && done===1'b0, "framerr");
clr=1; tick; clr=0; tick;
chk(fe===1'b0, "clr_fe");
// parity: 8E1, byte 0x03 has even ones(2)->parity 0 for even. send correct parity
fmt=3'b010;
// 0x03 = ones count 2 (even) -> even parity bit = 0
send_bit(0); data=8'h03; for(i=0;i<8;i=i+1) send_bit(data[i]); send_bit(0); send_bit(1);
repeat(2) tick;
chk(ob===8'h03 && cnt===8'd4 && pe===1'b0, "even_ok");
ack=1; tick; ack=0; tick;
// now send wrong parity: parity bit=1 for 0x03 even -> parity error
send_bit(0); data=8'h03; for(i=0;i<8;i=i+1) send_bit(data[i]); send_bit(1); send_bit(1);
repeat(2) tick;
chk(pe===1'b1 && cnt===8'd4 && done===1'b0, "even_err");
clr=1; tick; clr=0; tick;
// 7N1 masks bit7
fmt=3'b001;
send_bit(0); data=8'hFF; for(i=0;i<7;i=i+1) send_bit(data[i]); send_bit(1);
repeat(2) tick;
chk(ob===8'h7F, "7n1_mask");
// start abort: falling edge then high at midpoint
fmt=3'b000;
in=0; repeat(4) tick; in=1; repeat(20) tick;
chk(done===ob==8'h7f? done:done, "abort_noflag"); // just ensure no crash
chk(pe===1'b0, "abort_pe");
if(fails==0) $display("ALL PASS"); else $display("%0d FAILURES",fails);
$finish;
end
endmodule
EOF
iverilog -g2012 -o t.out /app/dut.sv tb.sv 2>&1 && vvp t.out 2>&1Exit code 2 tb.sv:69: warning: Extra digits given for sized hex constant. tb.sv:69: warning: Numeric constant truncated to 8 bits. tb.sv:69: syntax error tb.sv:69: error: Syntax error in task arguments. [error] tool reported failure
/tmp/tb.sv
in=0; repeat(4) tick; in=1; repeat(20) tick;
chk(done===ob==8'h7f? done:done, "abort_noflag"); // just ensure no crash
chk(pe===1'b0, "abort_pe"); in=0; repeat(4) tick; in=1; repeat(20) tick;
chk(pe===1'b0 && fe===1'b0, "abort_noflag");cd /tmp && iverilog -g2012 -o t.out /app/dut.sv tb.sv 2>&1 | grep -v truncat && vvp t.out 2>&1
Exit code 1 [error] tool reported failure
cd /tmp && iverilog -g2012 -o t.out /app/dut.sv tb.sv 2>&1; echo "---run---"; vvp t.out 2>&1
---run--- ALL PASS tb.sv:72: $finish called at 12056000 (1ps) Shell cwd was reset to /app [stdout] ---run--- ALL PASS tb.sv:72: $finish called at 12056000 (1ps) [stderr] Shell cwd was reset to /app
cd /tmp && cat > tbb.sv <<'EOF'
`timescale 1ns/1ps
module tbb;
reg clk=0, reset=1, in=1; reg [15:0] baud=1; reg [2:0] fmt=0; reg clr=0, ack=0;
wire [7:0] ob; wire done, pe, fe, brk, ovf; wire [7:0] cnt;
TopModule d(clk,reset,in,baud,fmt,clr,ack,ob,done,pe,fe,brk,ovf,cnt);
always #5 clk=~clk;
integer i, fails=0; reg [7:0] data;
task tick; begin @(posedge clk); #1; end endtask
task send_bit(input b); integer j; begin in=b; repeat(16) tick; end endtask
initial begin
tick; tick; reset=0; in=1; repeat(4) tick;
// break: threshold 176*1=176 low clocks
in=0;
for(i=0;i<175;i=i+1) tick;
if(brk!==1'b0) begin $display("FAIL brk_early i=%0d",i); fails=fails+1; end
tick; // 176th low clock -> assert
if(brk!==1'b1) begin $display("FAIL brk_assert"); fails=fails+1; end
// go high, one clock later deassert
in=1; tick;
if(brk!==1'b0) begin $display("FAIL brk_deassert"); fails=fails+1; end
repeat(4) tick;
// 8N2 good frame: two stop bits high, count increments
fmt=3'b100;
send_bit(0); data=8'hC3; for(i=0;i<8;i=i+1) send_bit(data[i]); send_bit(1); send_bit(1);
repeat(2) tick;
if(!(ob===8'hC3 && done===1'b1 && cnt===8'd1 && fe===0)) begin $display("FAIL 8n2 ob=%h done=%b cnt=%d fe=%b",ob,done,cnt,fe); fails=fails+1; end
ack=1; tick; ack=0; tick;
// 8N2 with second stop low -> frame_err, consumes both slots, no commit
send_bit(0); data=8'h11; for(i=0;i<8;i=i+1) send_bit(data[i]); send_bit(1); send_bit(0);
repeat(2) tick;
if(!(fe===1'b1 && cnt===8'd1 && done===1'b0)) begin $display("FAIL 8n2bad fe=%b cnt=%d done=%b",fe,cnt,done); fails=fails+1; end
if(fails==0) $display("ALL PASS"); else $display("%0d FAIL",fails);
$finish;
end
endmodule
EOF
iverilog -g2012 -o tb.out /app/dut.sv tbb.sv 2>&1; echo ---; vvp tb.out 2>&1--- FAIL 8n2 ob=c3 done=1 cnt= 1 fe=1 1 FAIL tbb.sv:36: $finish called at 5446000 (1ps) Shell cwd was reset to /app [stdout] --- FAIL 8n2 ob=c3 done=1 cnt= 1 fe=1 1 FAIL tbb.sv:36: $finish called at 5446000 (1ps) [stderr] Shell cwd was reset to /app
/tmp/tbb.sv
in=1; tick;
if(brk!==1'b0) begin $display("FAIL brk_deassert"); fails=fails+1; end
repeat(4) tick; in=1; tick;
if(brk!==1'b0) begin $display("FAIL brk_deassert"); fails=fails+1; end
repeat(30) tick; // let the break-induced frame finish
clr=1; ack=1; tick; clr=0; ack=0; tick; // clear sticky flags + done from break frame
repeat(4) tick;/tmp/tbb.sv
1 `timescale 1ns/1ps 2 module tbb; 3 reg clk=0, reset=1, in=1; reg [15:0] baud=1; reg [2:0] fmt=0; reg clr=0, ack=0; 4 wire [7:0] ob; wire done, pe, fe, brk, ovf; wire [7:0] cnt; 5 TopModule d(clk,reset,in,baud,fmt,clr,ack,ob,done,pe,fe,brk,ovf,cnt);
cd /tmp && python3 - <<'PY'
s=open('tbb.sv').read()
s=s.replace(
""" in=1; tick;
if(brk!==1'b0) begin $display("FAIL brk_deassert"); fails=fails+1; end
repeat(4) tick;""",
""" in=1; tick;
if(brk!==1'b0) begin $display("FAIL brk_deassert"); fails=fails+1; end
repeat(30) tick;
clr=1; ack=1; tick; clr=0; ack=0; tick;
repeat(4) tick;""")
open('tbb.sv','w').write(s)
print("patched")
PY
iverilog -g2012 -o tb.out /app/dut.sv tbb.sv 2>&1; echo ---; vvp tb.out 2>&1patched --- ALL PASS tbb.sv:38: $finish called at 5766000 (1ps) Shell cwd was reset to /app [stdout] patched --- ALL PASS tbb.sv:38: $finish called at 5766000 (1ps) [stderr] Shell cwd was reset to /app
(verilator --lint-only -Wall -Wno-DECLFILENAME dut.sv 2>&1 | head -30; echo "exit:$?") ; rm -f /tmp/tb*.sv /tmp/*.out /tmp/dutd.sv 2>/dev/null; echo cleaned
/bin/bash: line 1: verilator: command not found exit:0 cleaned [stdout] /bin/bash: line 1: verilator: command not found exit:0 cleaned
No file changes, the agent left the workspace untouched.
TEST dut_present: PASS (/app/dut.sv exists) TEST dut_forbidden: PASS (no forbidden constructs) TEST harness_prepare: PASS (harness names nonce-renamed) TEST dut_compiles: PASS (compiled with held-back reference/testbench) TEST simulation_completed: PASS (Mismatches: 10 in 155243 samples) TEST reference_equivalence: FAIL (10 mismatches in 155243 samples)
Reproduce this trial: git checkout 2f94510 && PYTHONPATH=src python3 scripts/build_site.py , then open trial/trial_21bdeeba99544630. Re-running the agent live requires EVAL_PLATFORM_ENABLE_OAUTH_SMOKE=1 and is non-deterministic.
Trial trial_21bdeeba99544630 · verifier authoritative; classifier explanatory.