tests/test.sh exit code (0 → resolved); the classification below is post-hoc and cannot change it.// UART receiver with configurable frame format, parity/framing error
// reporting, overflow tracking, and break detection.
module TopModule(
input logic clk,
input logic reset,
input logic in,
input logic [15:0] baud_div_i,
input logic [2:0] frame_fmt_i,
input logic clear_err_i,
input logic data_ack_i,
output logic [7:0] out_byte,
output logic done,
output logic parity_err_o,
output logic frame_err_o,
output logic break_o,
output logic ovf_o,
output logic [7:0] byte_count_o
);
// Receiver states
localparam logic [2:0] S_IDLE = 3'd0,
S_START = 3'd1,
S_DATA = 3'd2,
S_PAR = 3'd3,
S_STOP = 3'd4;
logic [2:0] state;
logic prev_in;
// Latched-on-start configuration
logic [15:0] l_baud; // >= 1
logic [3:0] l_ndata; // 7 or 8
logic l_haspar;
logic l_parodd;
logic [1:0] l_nstop; // 1 or 2
// Per-bit timing / bookkeeping
logic [19:0] cnt;
logic [3:0] bit_idx;
logic [1:0] stop_idx;
logic [7:0] data_reg;
logic par_acc;
logic frame_bad;
// Break detector (uses live baud)
logic [31:0] low_cnt;
// Bit-period timing derived from latched baud
logic [19:0] period, half;
assign period = {l_baud, 4'b0}; // 16 * l_baud
assign half = {1'b0, l_baud, 3'b0}; // 8 * l_baud
wire midpoint = (cnt == (half - 20'd1));
wire endbit = (cnt == (period - 20'd1));
// Break threshold: 11 * 16 * live baud
wire [31:0] brk_thresh = 32'd176 * baud_div_i;
always_ff @(posedge clk) begin
if (reset) begin
state <= S_IDLE;
prev_in <= 1'b1;
out_byte <= 8'd0;
done <= 1'b0;
parity_err_o <= 1'b0;
frame_err_o <= 1'b0;
break_o <= 1'b0;
ovf_o <= 1'b0;
byte_count_o <= 8'd0;
low_cnt <= 32'd0;
cnt <= 20'd0;
bit_idx <= 4'd0;
stop_idx <= 2'd0;
data_reg <= 8'd0;
par_acc <= 1'b0;
frame_bad <= 1'b0;
l_baud <= 16'd1;
l_ndata <= 4'd8;
l_haspar <= 1'b0;
l_parodd <= 1'b0;
l_nstop <= 2'd1;
end else begin
prev_in <= in;
// ---- Break detector (independent of frame FSM, live baud) ----
if (in) begin
low_cnt <= 32'd0;
break_o <= 1'b0; // deasserts one clock after high
end else begin
if (low_cnt != 32'hFFFF_FFFF)
low_cnt <= low_cnt + 32'd1;
if ((baud_div_i != 16'd0) && ((low_cnt + 32'd1) >= brk_thresh))
break_o <= 1'b1;
end
// ---- Sticky error clear (same-cycle error/overflow overrides) ----
if (clear_err_i) begin
parity_err_o <= 1'b0;
frame_err_o <= 1'b0;
ovf_o <= 1'b0;
end
// ---- Done ack (a commit this cycle overrides this clear) ----
if (data_ack_i)
done <= 1'b0;
// ---- Frame receive FSM ----
case (state)
S_IDLE: begin
if (prev_in && !in) begin
// Idle high-to-low transition: start a frame, latch config
l_baud <= (baud_div_i == 16'd0) ? 16'd1 : baud_div_i;
case (frame_fmt_i)
3'b000: begin l_ndata<=4'd8; l_haspar<=1'b0; l_parodd<=1'b0; l_nstop<=2'd1; end
3'b001: begin l_ndata<=4'd7; l_haspar<=1'b0; l_parodd<=1'b0; l_nstop<=2'd1; end
3'b010: begin l_ndata<=4'd8; l_haspar<=1'b1; l_parodd<=1'b0; l_nstop<=2'd1; end
3'b011: begin l_ndata<=4'd8; l_haspar<=1'b1; l_parodd<=1'b1; l_nstop<=2'd1; end
3'b100: begin l_ndata<=4'd8; l_haspar<=1'b0; l_parodd<=1'b0; l_nstop<=2'd2; end
default: begin l_ndata<=4'd8; l_haspar<=1'b0; l_parodd<=1'b0; l_nstop<=2'd1; end
endcase
state <= S_START;
cnt <= 20'd0;
bit_idx <= 4'd0;
stop_idx <= 2'd0;
data_reg <= 8'd0;
par_acc <= 1'b0;
frame_bad <= 1'b0;
end
end
S_START: begin
if (midpoint && in) begin
// High start midpoint: abort with no flags
state <= S_IDLE;
cnt <= 20'd0;
end else if (endbit) begin
state <= S_DATA;
cnt <= 20'd0;
bit_idx <= 4'd0;
end else begin
cnt <= cnt + 20'd1;
end
end
S_DATA: begin
if (midpoint) begin
data_reg[bit_idx] <= in;
par_acc <= par_acc ^ in;
end
if (endbit) begin
cnt <= 20'd0;
if (bit_idx == (l_ndata - 4'd1)) begin
if (l_haspar)
state <= S_PAR;
else begin
state <= S_STOP;
stop_idx <= 2'd0;
end
end else begin
bit_idx <= bit_idx + 4'd1;
end
end else begin
cnt <= cnt + 20'd1;
end
end
S_PAR: begin
if (midpoint) begin
// Even -> XOR(data,parity)=0 ; Odd -> XOR=1
if ((par_acc ^ in) != l_parodd) begin
parity_err_o <= 1'b1;
frame_bad <= 1'b1;
end
end
if (endbit) begin
cnt <= 20'd0;
state <= S_STOP;
stop_idx <= 2'd0;
end else begin
cnt <= cnt + 20'd1;
end
end
S_STOP: begin
if (midpoint) begin
if (!in) begin
frame_err_o <= 1'b1;
frame_bad <= 1'b1;
end
end
if (endbit) begin
cnt <= 20'd0;
if (stop_idx == (l_nstop - 2'd1)) begin
// Final stop slot complete
if (!frame_bad) begin
out_byte <= data_reg;
byte_count_o <= (byte_count_o == 8'hFF) ? 8'hFF
: byte_count_o + 8'd1;
if (done && !data_ack_i)
ovf_o <= 1'b1; // good commit over unacked done
done <= 1'b1; // commit wins over ack-clear
end
state <= S_IDLE;
end else begin
stop_idx <= stop_idx + 2'd1;
end
end else begin
cnt <= cnt + 20'd1;
end
end
default: state <= S_IDLE;
endcase
end
end
endmodule
Compile/lint the SystemVerilog module
(which iverilog verilator 2>/dev/null; iverilog -g2012 -o /tmp/dut.out dut.sv 2>&1 && echo "IVERILOG OK") || echo "no iverilog"; verilator --lint-only -Wall -sv dut.sv 2>&1 | head -40 || true
/usr/bin/iverilog IVERILOG OK /bin/bash: line 1: verilator: command not found [stdout] /usr/bin/iverilog IVERILOG OK /bin/bash: line 1: verilator: command not found
No file changes, the agent left the workspace untouched.
TEST dut_present: PASS (/app/dut.sv exists) TEST dut_forbidden: PASS (no forbidden constructs) TEST harness_prepare: PASS (harness names nonce-renamed) TEST dut_compiles: PASS (compiled with held-back reference/testbench) TEST simulation_completed: PASS (Mismatches: 0 in 155243 samples) TEST reference_equivalence: PASS (all 155243 samples matched reference)
Reproduce this trial: git checkout 2f94510 && PYTHONPATH=src python3 scripts/build_site.py , then open trial/trial_3c02a8a158084f26. Re-running the agent live requires EVAL_PLATFORM_ENABLE_OAUTH_SMOKE=1 and is non-deterministic.
Trial trial_3c02a8a158084f26 · verifier authoritative; classifier explanatory.