tests/test.sh exit code (0 → resolved); the classification below is post-hoc and cannot change it.// UART-style serial receiver.
// Synchronous active-high reset. Serial line idles high.
module TopModule(
input logic clk,
input logic reset,
input logic in,
input logic [15:0] baud_div_i,
input logic [2:0] frame_fmt_i,
input logic clear_err_i,
input logic data_ack_i,
output logic [7:0] out_byte,
output logic done,
output logic parity_err_o,
output logic frame_err_o,
output logic break_o,
output logic ovf_o,
output logic [7:0] byte_count_o
);
// ---------------- State ----------------
logic active; // frame in progress
logic [31:0] clk_cnt; // clock counter within current bit
logic [4:0] bit_num; // 0=start, 1..N=data, parity, stop bits
logic [7:0] data_sr; // received data bits (LSB first)
logic frm_bad; // this frame had a parity or framing error
// Latched (per-frame) parameters
logic [15:0] baud_lat;
logic [3:0] l_ndata;
logic l_haspar;
logic l_parodd;
logic [1:0] l_nstop;
// Break detection / edge detection
logic in_q; // registered (previous) value of 'in'
logic [31:0] low_cnt; // consecutive-low clock counter (live baud)
// ---------------- Derived (combinational) ----------------
// Live baud (clamped to >=1) for break timing.
wire [15:0] baud_use = (baud_div_i == 16'd0) ? 16'd1 : baud_div_i;
wire [31:0] brk_thr = 32'd176 * {16'd0, baud_use}; // 11 * 16 * baud
wire [31:0] bit_clocks = {16'd0, baud_lat} << 4; // 16 * latched baud
wire [31:0] mid = {16'd0, baud_lat} << 3; // midpoint sample
// Bit boundaries for the latched format
wire [4:0] parity_num = {1'b0, l_ndata} + 5'd1;
wire [4:0] first_stop = {1'b0, l_ndata} + 5'd1 + (l_haspar ? 5'd1 : 5'd0);
wire [4:0] last_num = {1'b0, l_ndata} + (l_haspar ? 5'd1 : 5'd0) + {3'd0, l_nstop};
// Events / classification
wire sample_now = active & (clk_cnt == mid);
wire bit_end = active & (clk_cnt == (bit_clocks - 32'd1));
wire is_start = (bit_num == 5'd0);
wire is_data = (bit_num >= 5'd1) & (bit_num <= {1'b0, l_ndata});
wire is_parity = l_haspar & (bit_num == parity_num);
wire is_stop = (bit_num >= first_stop) & (bit_num <= last_num);
// Parity check: even -> XOR(data,parity)=0 ; odd -> XOR(data,parity)=1
wire xor_all = (^data_sr) ^ in;
wire par_fail = l_parodd ? (xor_all == 1'b0) : (xor_all == 1'b1);
// Combinational set conditions
wire par_set = sample_now & is_parity & par_fail; // parity midpoint failing
wire frm_set = sample_now & is_stop & ~in; // low stop midpoint
wire abort = sample_now & is_start & in; // high start midpoint
wire done_commit = bit_end & (bit_num == last_num) & ~frm_bad;
wire ovf_set = done_commit & done & ~data_ack_i;
always_ff @(posedge clk) begin
if (reset) begin
active <= 1'b0;
clk_cnt <= 32'd0;
bit_num <= 5'd0;
data_sr <= 8'd0;
frm_bad <= 1'b0;
baud_lat <= 16'd1;
l_ndata <= 4'd8;
l_haspar <= 1'b0;
l_parodd <= 1'b0;
l_nstop <= 2'd1;
in_q <= 1'b1;
low_cnt <= 32'd0;
out_byte <= 8'd0;
done <= 1'b0;
parity_err_o <= 1'b0;
frame_err_o <= 1'b0;
break_o <= 1'b0;
ovf_o <= 1'b0;
byte_count_o <= 8'd0;
end else begin
in_q <= in;
// ------------- Break detection (independent, live baud) -------------
if (in_q) begin
break_o <= 1'b0; // deassert one clock after high
end else if (low_cnt + 32'd1 >= brk_thr) begin
break_o <= 1'b1;
end
low_cnt <= in ? 32'd0
: ((low_cnt >= brk_thr) ? brk_thr : low_cnt + 32'd1);
// ------------- Receiver -------------
if (!active) begin
// Only an idle high-to-low transition starts a frame.
if (in_q & ~in) begin
active <= 1'b1;
clk_cnt <= 32'd0;
bit_num <= 5'd0;
data_sr <= 8'd0;
frm_bad <= 1'b0;
baud_lat <= (baud_div_i == 16'd0) ? 16'd1 : baud_div_i;
case (frame_fmt_i)
3'b001: begin l_ndata <= 4'd7; l_haspar <= 1'b0; l_parodd <= 1'b0; l_nstop <= 2'd1; end
3'b010: begin l_ndata <= 4'd8; l_haspar <= 1'b1; l_parodd <= 1'b0; l_nstop <= 2'd1; end
3'b011: begin l_ndata <= 4'd8; l_haspar <= 1'b1; l_parodd <= 1'b1; l_nstop <= 2'd1; end
3'b100: begin l_ndata <= 4'd8; l_haspar <= 1'b0; l_parodd <= 1'b0; l_nstop <= 2'd2; end
default: begin l_ndata <= 4'd8; l_haspar <= 1'b0; l_parodd <= 1'b0; l_nstop <= 2'd1; end
endcase
end
end else begin
// Sampling at bit midpoints
if (abort) begin
active <= 1'b0; // false start: no flags
end
if (sample_now & is_data) begin
data_sr[bit_num - 5'd1] <= in; // LSB first
end
if (par_set | frm_set) begin
frm_bad <= 1'b1;
end
// Advance through the bit period
if (bit_end) begin
if (bit_num == last_num) begin
active <= 1'b0; // return to idle after final stop slot
end else begin
bit_num <= bit_num + 5'd1;
clk_cnt <= 32'd0;
end
end else begin
clk_cnt <= clk_cnt + 32'd1;
end
end
// ------------- Sticky error/overflow flags (set wins over clear) -------------
parity_err_o <= par_set ? 1'b1 : (clear_err_i ? 1'b0 : parity_err_o);
frame_err_o <= frm_set ? 1'b1 : (clear_err_i ? 1'b0 : frame_err_o);
ovf_o <= ovf_set ? 1'b1 : (clear_err_i ? 1'b0 : ovf_o);
// ------------- Commit / done / count -------------
if (done_commit) begin
done <= 1'b1; // commit wins over ack this cycle
out_byte <= data_sr; // upper bits are 0 for 7-bit formats
byte_count_o <= (byte_count_o == 8'hFF) ? 8'hFF : (byte_count_o + 8'd1);
end else if (data_ack_i) begin
done <= 1'b0;
end
end
end
endmodule
Lint/compile the module
(iverilog -g2012 -o /tmp/dut.out dut.sv 2>&1 && echo "IVERILOG OK") || (verilator --lint-only -Wall -sv dut.sv 2>&1 && echo "VERILATOR OK") || echo "no simulator found"
IVERILOG OK [stdout] IVERILOG OK
No file changes, the agent left the workspace untouched.
TEST dut_present: PASS (/app/dut.sv exists) TEST dut_forbidden: PASS (no forbidden constructs) TEST harness_prepare: PASS (harness names nonce-renamed) TEST dut_compiles: PASS (compiled with held-back reference/testbench) TEST simulation_completed: PASS (Mismatches: 14 in 155243 samples) TEST reference_equivalence: FAIL (14 mismatches in 155243 samples)
Reproduce this trial: git checkout 2f94510 && PYTHONPATH=src python3 scripts/build_site.py , then open trial/trial_50abc581b9cb4c7d. Re-running the agent live requires EVAL_PLATFORM_ENABLE_OAUTH_SMOKE=1 and is non-deterministic.
Trial trial_50abc581b9cb4c7d · verifier authoritative; classifier explanatory.