tests/test.sh exit code (0 → resolved); the classification below is post-hoc and cannot change it.// UART-style serial receiver.
// Synchronizable, single clock domain, synchronous active-high reset.
module TopModule (
input wire clk,
input wire reset,
input wire in,
input wire [15:0] baud_div_i,
input wire [2:0] frame_fmt_i,
input wire clear_err_i,
input wire data_ack_i,
output reg [7:0] out_byte,
output reg done,
output reg parity_err_o,
output reg frame_err_o,
output reg break_o,
output reg ovf_o,
output reg [7:0] byte_count_o
);
// ---- state encoding ----
localparam [2:0] S_IDLE = 3'd0;
localparam [2:0] S_START = 3'd1;
localparam [2:0] S_DATA = 3'd2;
localparam [2:0] S_PAR = 3'd3;
localparam [2:0] S_STOP = 3'd4;
reg [2:0] state;
// ---- latched frame parameters ----
reg [15:0] baud_l; // >= 1
reg seven; // 7 data bits
reg par_en;
reg par_odd;
reg two_stop;
// ---- receive datapath ----
reg [20:0] cnt; // clock counter within a bit
reg [3:0] bit_idx; // data bit index
reg [1:0] stop_idx; // stop slot index
reg [7:0] data_buf; // received data (LSB-first)
reg frm_perr; // this-frame parity error
reg frm_ferr; // this-frame framing error
reg prev_in; // previous serial level for edge detect
// ---- break detector (uses live baud) ----
reg [24:0] low_count;
// bit timing (16*baud full, 8*baud half); stable within a frame
wire [20:0] full = {baud_l, 4'b0000}; // 16 * baud_l
wire [20:0] half = {baud_l, 3'b000}; // 8 * baud_l
// live break threshold: 11 * 16 * (nonzero live baud) = 176 * baud
wire [15:0] bbaud = (baud_div_i == 16'd0) ? 16'd1 : baud_div_i;
wire [24:0] brk_thresh = bbaud * 25'd176;
always @(posedge clk) begin : main
reg comm; // good-frame commit this cycle
reg pev; // parity error event this cycle
reg fev; // framing error event this cycle
reg oev; // overflow event this cycle
reg comp; // parity accumulator
comm = 1'b0;
pev = 1'b0;
fev = 1'b0;
oev = 1'b0;
comp = 1'b0;
if (reset) begin
state <= S_IDLE;
baud_l <= 16'd1;
seven <= 1'b0;
par_en <= 1'b0;
par_odd <= 1'b0;
two_stop <= 1'b0;
cnt <= 21'd0;
bit_idx <= 4'd0;
stop_idx <= 2'd0;
data_buf <= 8'd0;
frm_perr <= 1'b0;
frm_ferr <= 1'b0;
prev_in <= 1'b1;
low_count <= 25'd0;
out_byte <= 8'd0;
done <= 1'b0;
parity_err_o <= 1'b0;
frame_err_o <= 1'b0;
break_o <= 1'b0;
ovf_o <= 1'b0;
byte_count_o <= 8'd0;
end else begin
prev_in <= in;
// -------- break detection (independent of frame reception) --------
if (!in) begin
if (low_count < brk_thresh)
low_count <= low_count + 25'd1;
break_o <= ((low_count + 25'd1) >= brk_thresh);
end else begin
low_count <= 25'd0;
break_o <= 1'b0; // deasserts one clock after high
end
// -------- receive FSM --------
case (state)
S_IDLE: begin
cnt <= 21'd0;
if (prev_in && !in) begin
// latch baud (0 -> 1) and format on the start edge
baud_l <= (baud_div_i == 16'd0) ? 16'd1 : baud_div_i;
case (frame_fmt_i)
3'b001: begin seven<=1'b1; par_en<=1'b0; par_odd<=1'b0; two_stop<=1'b0; end // 7N1
3'b010: begin seven<=1'b0; par_en<=1'b1; par_odd<=1'b0; two_stop<=1'b0; end // 8E1
3'b011: begin seven<=1'b0; par_en<=1'b1; par_odd<=1'b1; two_stop<=1'b0; end // 8O1
3'b100: begin seven<=1'b0; par_en<=1'b0; par_odd<=1'b0; two_stop<=1'b1; end // 8N2
default: begin seven<=1'b0; par_en<=1'b0; par_odd<=1'b0; two_stop<=1'b0; end // 8N1
endcase
data_buf <= 8'd0;
frm_perr <= 1'b0;
frm_ferr <= 1'b0;
bit_idx <= 4'd0;
stop_idx <= 2'd0;
cnt <= 21'd0;
state <= S_START;
end
end
S_START: begin
if (cnt == half && in) begin
// high start midpoint: false start, abort with no flags
state <= S_IDLE;
cnt <= 21'd0;
end else if (cnt == full - 21'd1) begin
cnt <= 21'd0;
bit_idx <= 4'd0;
state <= S_DATA;
end else begin
cnt <= cnt + 21'd1;
end
end
S_DATA: begin
if (cnt == half) begin
data_buf[bit_idx] <= in;
cnt <= cnt + 21'd1;
end else if (cnt == full - 21'd1) begin
cnt <= 21'd0;
if (bit_idx == (seven ? 4'd6 : 4'd7)) begin
if (par_en) begin
state <= S_PAR;
end else begin
stop_idx <= 2'd0;
state <= S_STOP;
end
end else begin
bit_idx <= bit_idx + 4'd1;
end
end else begin
cnt <= cnt + 21'd1;
end
end
S_PAR: begin
if (cnt == half) begin
comp = (^data_buf) ^ in; // XOR of data and parity bit
pev = comp ^ par_odd; // even: err if comp=1; odd: err if comp=0
if (pev) frm_perr <= 1'b1;
cnt <= cnt + 21'd1;
end else if (cnt == full - 21'd1) begin
cnt <= 21'd0;
stop_idx <= 2'd0;
state <= S_STOP;
end else begin
cnt <= cnt + 21'd1;
end
end
S_STOP: begin
if (cnt == half) begin
if (!in) begin
fev = 1'b1; // low stop midpoint: framing error
frm_ferr <= 1'b1;
end
cnt <= cnt + 21'd1;
end else if (cnt == full - 21'd1) begin
if (stop_idx == (two_stop ? 2'd1 : 2'd0)) begin
// final stop slot completes
if (!frm_perr && !frm_ferr)
comm = 1'b1; // good frame commits
cnt <= 21'd0;
state <= S_IDLE;
end else begin
stop_idx <= stop_idx + 2'd1;
cnt <= 21'd0;
end
end else begin
cnt <= cnt + 21'd1;
end
end
default: state <= S_IDLE;
endcase
// -------- sticky error / overflow flags (event wins over clear) --------
oev = comm && done && !data_ack_i;
if (pev) parity_err_o <= 1'b1;
else if (clear_err_i) parity_err_o <= 1'b0;
if (fev) frame_err_o <= 1'b1;
else if (clear_err_i) frame_err_o <= 1'b0;
if (oev) ovf_o <= 1'b1;
else if (clear_err_i) ovf_o <= 1'b0;
// -------- done (commit sets; else ack clears) --------
if (comm) done <= 1'b1;
else if (data_ack_i) done <= 1'b0;
// -------- committed byte and saturating count --------
if (comm) begin
out_byte <= seven ? {1'b0, data_buf[6:0]} : data_buf;
byte_count_o <= (byte_count_o == 8'hFF) ? 8'hFF : (byte_count_o + 8'd1);
end
end
end
endmodule
Lint/compile the SystemVerilog
(iverilog -g2012 -o /tmp/dut_test dut.sv 2>&1 && echo "IVERILOG OK") || (verilator --lint-only -Wno-fatal --sv dut.sv 2>&1 && echo "VERILATOR OK") || echo "no simulator available"
IVERILOG OK [stdout] IVERILOG OK
Run basic 8N1 sanity test
cat > /tmp/tb.sv <<'EOF'
module tb;
reg clk=0, reset=1, in=1, clear_err_i=0, data_ack_i=0;
reg [15:0] baud_div_i=1;
reg [2:0] frame_fmt_i=0;
wire [7:0] out_byte; wire done, parity_err_o, frame_err_o, break_o, ovf_o;
wire [7:0] byte_count_o;
TopModule d(clk,reset,in,baud_div_i,frame_fmt_i,clear_err_i,data_ack_i,
out_byte,done,parity_err_o,frame_err_o,break_o,ovf_o,byte_count_o);
always #1 clk=~clk;
integer i;
// send one bit = 16 clocks (baud=1)
task send_bit(input b); begin in=b; repeat(16) @(posedge clk); end endtask
reg [7:0] data = 8'hA5; // 10100101
initial begin
@(posedge clk); reset<=0; @(posedge clk);
// 8N1 frame: start(0), 8 data LSB first, stop(1)
send_bit(0);
for(i=0;i<8;i=i+1) send_bit(data[i]);
send_bit(1);
repeat(4) @(posedge clk);
$display("out_byte=%h done=%b count=%d perr=%b ferr=%b", out_byte,done,byte_count_o,parity_err_o,frame_err_o);
if (out_byte==8'hA5 && done && byte_count_o==1) $display("PASS 8N1");
else $display("FAIL 8N1");
$finish;
end
endmodule
EOF
iverilog -g2012 -o /tmp/t /app/dut.sv /tmp/tb.sv && vvp /tmp/tout_byte=a5 done=1 count= 1 perr=0 ferr=0 PASS 8N1 /tmp/tb.sv:24: $finish called at 331 (1s) [stdout] out_byte=a5 done=1 count= 1 perr=0 ferr=0 PASS 8N1 /tmp/tb.sv:24: $finish called at 331 (1s)
Test parity, framing, overflow, break
cat > /tmp/tb2.sv <<'EOF'
module tb;
reg clk=0, reset=1, in=1, clear_err_i=0, data_ack_i=0;
reg [15:0] baud_div_i=1;
reg [2:0] frame_fmt_i=0;
wire [7:0] out_byte; wire done, parity_err_o, frame_err_o, break_o, ovf_o;
wire [7:0] byte_count_o;
TopModule d(clk,reset,in,baud_div_i,frame_fmt_i,clear_err_i,data_ack_i,
out_byte,done,parity_err_o,frame_err_o,break_o,ovf_o,byte_count_o);
always #1 clk=~clk;
integer i;
task send_bit(input b); begin in=b; repeat(16) @(posedge clk); end endtask
task frame8(input [7:0] dat, input pbit, input stopok); begin
send_bit(0);
for(i=0;i<8;i=i+1) send_bit(dat[i]);
if(frame_fmt_i==3'b010||frame_fmt_i==3'b011) send_bit(pbit);
send_bit(stopok);
if(frame_fmt_i==3'b100) send_bit(1); // 2nd stop
end endtask
initial begin
@(posedge clk); reset<=0; @(posedge clk);
// 8E1 correct parity for A5 (^A5 = 0), even wants xor=0 -> parity bit=0
frame_fmt_i=3'b010;
frame8(8'hA5,1'b0,1'b1); repeat(4) @(posedge clk);
$display("8E1 good: byte=%h done=%b perr=%b cnt=%d",out_byte,done,parity_err_o,byte_count_o);
// 8E1 wrong parity -> parity bit=1 (should error, no commit)
data_ack_i=1;@(posedge clk);data_ack_i=0; // clear done
frame8(8'h5A,1'b0,1'b1); // ^5A=0, even wants pbit=0, send 1 -> error
repeat(4) @(posedge clk);
$display("8E1 bad : perr=%b done=%b cnt=%d",parity_err_o,done,byte_count_o);
// clear errors
clear_err_i=1;@(posedge clk);clear_err_i=0;
$display("after clear perr=%b",parity_err_o);
// framing error: 8N1 with low stop
frame_fmt_i=3'b000;
frame8(8'h3C,1'b0,1'b0); repeat(4) @(posedge clk);
$display("ferr: frame_err=%b cnt=%d",frame_err_o,byte_count_o);
clear_err_i=1;@(posedge clk);clear_err_i=0;
// overflow: two good frames without ack (done already set from first 8E1? cnt currently 1)
// ensure done low first
data_ack_i=1;@(posedge clk);data_ack_i=0;
frame8(8'h11,1'b0,1'b1); repeat(4) @(posedge clk); // commit -> done=1
$display("frameA done=%b byte=%h ovf=%b",done,out_byte,ovf_o);
frame8(8'h22,1'b0,1'b1); repeat(4) @(posedge clk); // done already high, no ack -> ovf
$display("frameB done=%b byte=%h ovf=%b (expect ovf=1 byte=22)",done,out_byte,ovf_o);
// break: hold low long. baud_div_i live=1 -> thresh=176 clks
clear_err_i=1;@(posedge clk);clear_err_i=0;
in=0; repeat(200) @(posedge clk);
$display("break while low=%b (expect 1)",break_o);
in=1; @(posedge clk); @(posedge clk);
$display("break after high=%b (expect 0)",break_o);
$finish;
end
endmodule
EOF
iverilog -g2012 -o /tmp/t2 /app/dut.sv /tmp/tb2.sv && vvp /tmp/t28E1 good: byte=a5 done=1 perr=0 cnt= 1 8E1 bad : perr=0 done=1 cnt= 2 after clear perr=0 ferr: frame_err=1 cnt= 2 frameA done=0 byte=5a ovf=0 frameB done=0 byte=5a ovf=0 (expect ovf=1 byte=22) break while low=1 (expect 1) break after high=0 (expect 0) /tmp/tb2.sv:57: $finish called at 2121 (1s) [stdout] 8E1 good: byte=a5 done=1 perr=0 cnt= 1 8E1 bad : perr=0 done=1 cnt= 2 after clear perr=0 ferr: frame_err=1 cnt= 2 frameA done=0 byte=5a ovf=0 frameB done=0 byte=5a ovf=0 (expect ovf=1 byte=22) break while low=1 (expect 1) break after high=0 (expect 0) /tmp/tb2.sv:57: $finish called at 2121 (1s)
Clean overflow and framing error test
cat > /tmp/tb3.sv <<'EOF'
module tb;
reg clk=0, reset=1, in=1, clear_err_i=0, data_ack_i=0;
reg [15:0] baud_div_i=1;
reg [2:0] frame_fmt_i=3'b000;
wire [7:0] out_byte; wire done, parity_err_o, frame_err_o, break_o, ovf_o;
wire [7:0] byte_count_o;
TopModule d(clk,reset,in,baud_div_i,frame_fmt_i,clear_err_i,data_ack_i,
out_byte,done,parity_err_o,frame_err_o,break_o,ovf_o,byte_count_o);
always #1 clk=~clk;
integer i;
task send_bit(input b); begin in=b; repeat(16) @(posedge clk); end endtask
task idle; begin in=1; repeat(20) @(posedge clk); end endtask
task frame(input [7:0] dat); begin
send_bit(0);
for(i=0;i<8;i=i+1) send_bit(dat[i]);
send_bit(1);
end endtask
initial begin
@(posedge clk); reset<=0; idle;
frame(8'h11); repeat(4) @(posedge clk);
$display("A: done=%b byte=%h ovf=%b cnt=%d (done=1,byte=11)",done,out_byte,ovf_o,byte_count_o);
idle;
// no ack -> old done high, commit again -> overflow, byte replaced
frame(8'h22); repeat(4) @(posedge clk);
$display("B: done=%b byte=%h ovf=%b cnt=%d (ovf=1,byte=22,cnt=2)",done,out_byte,ovf_o,byte_count_o);
// ack clears done
data_ack_i=1;@(posedge clk);data_ack_i=0;
$display("C: done=%b (expect 0)",done);
// framing error frame (low stop), then idle
idle;
send_bit(0); for(i=0;i<8;i=i+1) send_bit(1'b1); send_bit(0); // low stop
repeat(4)@(posedge clk);
$display("D: frame_err=%b cnt=%d done=%b (ferr=1,cnt still 2,done 0)",frame_err_o,byte_count_o,done);
$finish;
end
endmodule
EOF
iverilog -g2012 -o /tmp/t3 /app/dut.sv /tmp/tb3.sv && vvp /tmp/t3A: done=1 byte=11 ovf=0 cnt= 1 (done=1,byte=11) B: done=1 byte=22 ovf=1 cnt= 2 (ovf=1,byte=22,cnt=2) C: done=0 (expect 0) D: frame_err=1 cnt= 2 done=0 (ferr=1,cnt still 2,done 0) /tmp/tb3.sv:34: $finish called at 1107 (1s) [stdout] A: done=1 byte=11 ovf=0 cnt= 1 (done=1,byte=11) B: done=1 byte=22 ovf=1 cnt= 2 (ovf=1,byte=22,cnt=2) C: done=0 (expect 0) D: frame_err=1 cnt= 2 done=0 (ferr=1,cnt still 2,done 0) /tmp/tb3.sv:34: $finish called at 1107 (1s)
No file changes, the agent left the workspace untouched.
TEST dut_present: PASS (/app/dut.sv exists) TEST dut_forbidden: PASS (no forbidden constructs) TEST harness_prepare: PASS (harness names nonce-renamed) TEST dut_compiles: PASS (compiled with held-back reference/testbench) TEST simulation_completed: PASS (Mismatches: 152164 in 155243 samples) TEST reference_equivalence: FAIL (152164 mismatches in 155243 samples)
Reproduce this trial: git checkout 2f94510 && PYTHONPATH=src python3 scripts/build_site.py , then open trial/trial_5bcc7b2f82424200. Re-running the agent live requires EVAL_PLATFORM_ENABLE_OAUTH_SMOKE=1 and is non-deterministic.
Trial trial_5bcc7b2f82424200 · verifier authoritative; classifier explanatory.